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Searched refs:FW_BLC_SELF_EN (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
A Dcdv_intel_display.c472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
A Dpsb_intel_reg.h567 #define FW_BLC_SELF_EN (1<<15) macro
/drivers/gpu/drm/i915/display/
A Di9xx_wm.c161 was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
162 intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
174 was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
175 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
176 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in _intel_set_memory_cxsr()
3765 wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
A Dintel_display_debugfs.c101 sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
/drivers/gpu/drm/i915/
A Di915_reg.h417 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ macro

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