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Searched refs:GATE (Results 1 – 25 of 44) sorted by relevance

12

/drivers/clk/samsung/
A Dclk-exynos5433.c2289 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2293 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2312 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2316 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2320 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2324 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2328 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
3913 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
4444 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
5242 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
[all …]
A Dclk-fsd.c837 GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
843 GATE(0,
911 GATE(0,
920 GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
929 GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
934 GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
1302 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
1310 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
1312 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
1314 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
[all …]
A Dclk-gs101.c1732 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1739 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1742 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1895 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
2194 GATE(CLK_GOUT_HSI0_PCLK,
3182 GATE(CLK_GOUT_MISC_GIC_GICCLK,
3246 GATE(CLK_GOUT_MISC_PUF_I_CLK,
3322 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
3374 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
3378 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
[all …]
A Dclk-exynos5250.c458 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
460 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
471 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
487 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
489 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
492 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
503 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
608 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
612 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
614 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
[all …]
A Dclk-exynos3250.c518 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
522 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
534 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
547 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
557 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
559 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
1032 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1034 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1036 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1050 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
[all …]
A Dclk-exynos7870.c503 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK,
507 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK,
523 GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
937 GATE(CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI,
940 GATE(CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI,
955 GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER,
959 GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER,
1099 GATE(CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL,
1103 GATE(CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK,
1700 GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK,
[all …]
A Dclk-exynos8895.c1684 GATE(CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK,
1692 GATE(CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK,
1771 GATE(CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK,
1812 GATE(CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK,
1967 GATE(CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK,
2024 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0,
2028 GATE(CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1,
2103 GATE(CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK,
2583 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
2591 GATE(CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK,
[all …]
A Dclk-s5pv210.c558 GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
570 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
577 GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
591 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
603 GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
629 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
647 GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
652 GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
680 GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
691 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
[all …]
A Dclk-exynos7.c793 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
850 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
950 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
954 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
1083 GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
1188 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1270 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1272 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1275 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1284 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
[all …]
A Dclk-exynos5420.c964 GATE(0, "aclk166", "mout_user_aclk166",
999 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
1001 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
1003 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1005 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1007 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1010 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1034 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1046 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1112 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
[all …]
A Dclk-exynos4.c745 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
751 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
799 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
801 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
908 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
910 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
912 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
939 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
943 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
981 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
[all …]
/drivers/clk/rockchip/
A Dclk-rk3368.c308 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
310 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
312 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
325 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
327 GATE(0, "gpll_ddr", "gpll", 0,
401 GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
461 GATE(0, "pclk_isp_in", "ext_isp", 0,
466 GATE(0, "pclk_vip_in", "ext_vip", 0,
628 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
630 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
[all …]
A Dclk-rk3399.c725 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
727 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
729 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
769 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
774 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
786 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
791 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
889 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
993 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
995 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
[all …]
A Dclk-rk3562.c263 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
276 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
278 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
280 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
282 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
284 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
315 GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0,
449 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0,
523 GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0,
972 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
[all …]
A Dclk-rk3228.c265 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
273 GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
275 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
277 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
354 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
356 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
358 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
360 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
362 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
402 GATE(0, "gpll_vop", "gpll", 0,
[all …]
A Dclk-rk3328.c300 GATE(0, "aclk_core_niu", "aclk_core", 0,
314 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
358 GATE(0, "pclk_bus", "pclk_bus_pre", 0,
360 GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
366 GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
478 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
480 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
531 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
533 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
541 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
[all …]
A Dclk-rv1108.c201 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
254 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
413 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
418 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
446 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
450 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
455 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
479 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
549 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
555 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
[all …]
A Dclk-rk3288.c319 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
323 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
328 GATE(0, "gpll_ddr", "gpll", 0,
350 GATE(0, "c2c_host", "aclk_cpu_src", 0,
394 GATE(0, "sclk_acc_efuse", "xin24m", 0,
397 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
399 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
401 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
575 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
645 GATE(0, "jtag", "ext_jtag", 0,
[all …]
A Dclk-rv1126.c367 GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
440 GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
577 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
579 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
581 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
735 GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
737 GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
742 GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
744 GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
757 GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
[all …]
A Dclk-rk3528.c310 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
320 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
330 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
340 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
350 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
360 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
370 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
501 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
559 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
843 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
[all …]
A Dclk-rk3588.c1052 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
1151 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1357 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
1451 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
1823 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
1825 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
2318 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
2330 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
2352 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
2398 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
[all …]
A Dclk-px30.c301 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
332 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
334 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
396 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
398 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
524 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
559 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
751 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
753 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
755 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
[all …]
A Dclk-rk3128.c209 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
219 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
238 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
288 GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0,
291 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
293 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
295 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
297 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
299 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
301 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
[all …]
A Dclk-rk3576.c726 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
760 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
764 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
768 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
772 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
901 GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0,
913 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0,
981 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
1067 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,
1069 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,
[all …]
/drivers/clk/pistachio/
A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
34 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
38 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
39 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
45 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
[all …]

Completed in 753 milliseconds

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