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Searched refs:GC (Results 1 – 25 of 55) sorted by relevance

123

/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v10_0.c340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
4480 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
4490 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
6635 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
7122 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, in gfx_v10_0_kiq_init_register()
8576 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, in gfx_v10_0_ring_set_wptr_gfx()
9436 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9439 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9446 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
[all …]
A Dimu_v11_0.c108 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode()
120 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode()
160 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v11_0_setup()
166 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); in imu_v11_0_setup()
174 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v11_0_start()
176 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); in imu_v11_0_start()
349 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_imu_rlc_ram()
352 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_imu_rlc_ram()
353 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); in program_imu_rlc_ram()
354 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); in program_imu_rlc_ram()
[all …]
A Dimu_v11_0_3.c34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
41 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
42 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
49 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
56 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
130 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_rlc_ram_register_setting()
131 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); in program_rlc_ram_register_setting()
132 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_rlc_ram_register_setting()
135 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_rlc_ram_register_setting()
136 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); in program_rlc_ram_register_setting()
[all …]
A Dimu_v12_0.c102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode()
114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode()
154 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v12_0_setup()
169 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); in imu_v12_0_start()
279 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_imu_rlc_ram_old()
281 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_imu_rlc_ram_old()
362 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_imu_rlc_ram()
373 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2); in imu_v12_0_program_rlc_ram()
390 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in imu_v12_0_program_rlc_ram()
391 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); in imu_v12_0_program_rlc_ram()
[all …]
A Dgfx_v9_4.c131 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
135 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
139 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
143 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
175 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
695 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
699 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
929 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
933 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
942 RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
[all …]
A Dgfxhub_v1_2.c94 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
97 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
101 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
104 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
108 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
111 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
115 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
118 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
297 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
300 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
[all …]
A Dgfx_v9_4_2.c785 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp); in gfx_v9_4_2_set_power_brake_sequence()
789 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); in gfx_v9_4_2_set_power_brake_sequence()
794 WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp); in gfx_v9_4_2_set_power_brake_sequence()
897 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
901 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
905 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
909 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
1806 WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX, in wave_read_ind()
1811 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
1871 status = RREG32_SOC15(GC, 0, in gfx_v9_4_2_query_sq_timeout_status()
[all …]
A Dgfxhub_v2_1.c162 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs()
220 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
231 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_1_init_cache_regs()
233 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
236 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_1_init_cache_regs()
248 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_1_init_cache_regs()
253 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_1_init_cache_regs()
257 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_1_init_cache_regs()
408 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_1_gart_disable()
471 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_1_init()
[all …]
A Dgfx_v9_0.c154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
165 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
166 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
167 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
168 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
169 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
170 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
210 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
218 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
3397 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); in gfx_v9_0_cp_gfx_resume()
[all …]
A Dgfx_v9_4_3.c1311 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1313 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1320 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1328 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1349 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); in gfx_v9_4_3_constants_init()
2030 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2036 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2563 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_sram_fgcg()
2572 WREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_sram_fgcg()
2585 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_repeater_fgcg()
[all …]
A Dgfxhub_v1_0.c115 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
121 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
147 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); in gfxhub_v1_0_init_system_aperture_regs()
179 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
188 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
190 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
193 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
205 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
367 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
420 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
[all …]
A Dgfxhub_v11_5_0.c159 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v11_5_0_init_system_aperture_regs()
218 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v11_5_0_init_cache_regs()
229 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v11_5_0_init_cache_regs()
234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v11_5_0_init_cache_regs()
246 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v11_5_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v11_5_0_init_cache_regs()
403 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v11_5_0_gart_disable()
418 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v11_5_0_set_fault_enable_default()
420 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v11_5_0_set_fault_enable_default()
471 SOC15_REG_OFFSET(GC, 0, in gfxhub_v11_5_0_init()
[all …]
A Dgfxhub_v12_0.c163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v12_0_init_system_aperture_regs()
223 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v12_0_init_cache_regs()
234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v12_0_init_cache_regs()
239 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v12_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v12_0_init_cache_regs()
256 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v12_0_init_cache_regs()
408 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v12_0_gart_disable()
423 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v12_0_set_fault_enable_default()
425 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v12_0_set_fault_enable_default()
476 SOC15_REG_OFFSET(GC, 0, in gfxhub_v12_0_init()
[all …]
A Dgfxhub_v3_0.c155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs()
215 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
226 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_init_cache_regs()
243 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs()
248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_init_cache_regs()
400 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
415 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v3_0_set_fault_enable_default()
417 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v3_0_set_fault_enable_default()
468 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_init()
[all …]
A Dgfxhub_v2_0.c157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
225 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
227 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
230 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
242 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
247 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_0_init_cache_regs()
382 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_0_gart_disable()
440 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
[all …]
A Dgfxhub_v3_0_3.c161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_3_init_system_aperture_regs()
220 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_3_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_3_init_cache_regs()
233 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_3_init_cache_regs()
236 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_3_init_cache_regs()
248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs()
253 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_3_init_cache_regs()
257 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_3_init_cache_regs()
393 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_3_gart_disable()
456 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_3_init()
[all …]
A Damdgpu_amdkfd_gfx_v9.c171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
290 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR, in kgd_gfx_v9_hqd_load()
493 act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_is_occupied()
636 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
909 *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), in kgd_gfx_v9_get_iq_wait_times()
965 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in get_wave_count()
1111 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1113 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1119 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1121 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, in kgd_gfx_v9_program_trap_handler_settings()
[all …]
A Dsdma_v5_0.c63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
[all …]
A Dgfx_v11_0.c173 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
975 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
985 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
2236 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
4447 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
5772 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
6694 tmp = RREG32_SOC15_IP(GC, target);
6697 WREG32_SOC15_IP(GC, target, tmp);
6704 tmp = RREG32_SOC15_IP(GC, target);
6707 WREG32_SOC15_IP(GC, target, tmp);
[all …]
A Dgfx_v12_0.c102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
819 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
829 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
1918 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v12_0_rlc_stop()
3341 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
[all …]
A Dsdma_v7_0.c63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL),
116 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
733 ic_op_cntl = RREG32_SOC15_IP(GC, in sdma_v7_0_load_microcode()
735 sdma_status = RREG32_SOC15_IP(GC, in sdma_v7_0_load_microcode()
[all …]
A Dsdma_v6_0.c64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
116 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
781 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); in sdma_v6_0_soft_reset()
[all …]
A Damdgpu_amdkfd_gfx_v10.c89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
151 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts()
263 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in kgd_hqd_load()
265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
273 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_hqd_load()
278 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, in kgd_hqd_load()
283 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
482 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
611 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
686 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); in kgd_wave_control_execute()
[all …]
A Dsdma_v5_2.c64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
[all …]
A Damdgpu_amdkfd_gfx_v10_3.c89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3()
120 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in init_interrupts_v10_3()
205 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value); in hqd_load_v10_3()
249 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in hqd_load_v10_3()
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in hqd_load_v10_3()
253 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in hqd_load_v10_3()
259 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in hqd_load_v10_3()
269 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in hqd_load_v10_3()
468 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_is_occupied_v10_3()
534 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_destroy_v10_3()
[all …]

Completed in 768 milliseconds

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