Home
last modified time | relevance | path

Searched refs:GET_INST (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dgfxhub_v1_2.c94 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
97 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
101 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
104 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
108 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
111 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
115 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
118 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
297 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
300 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
[all …]
A Dgfx_v9_4_3.c353 dev_inst = GET_INST(GC, i); in gfx_v9_4_3_init_golden_registers()
2030 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2036 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2336 GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_fini()
4399 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4408 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4429 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4465 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4470 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4487 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
[all …]
A Damdgpu_amdkfd_gfx_v9.c59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
636 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
909 *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), in kgd_gfx_v9_get_iq_wait_times()
1034 soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1072 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1111 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1113 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1119 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1121 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, in kgd_gfx_v9_program_trap_handler_settings()
[all …]
A Damdgpu_jpeg.h39 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
42 JPEG, GET_INST(JPEG, inst_idx), \
66 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
68 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
71 JPEG, GET_INST(JPEG, inst_idx), \
80 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
82 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
351 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, in kgd_gfx_v9_4_3_hqd_load()
355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
493 WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
[all …]
A Djpeg_v4_0_3.c173 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_sw_init()
276 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start_sriov()
397 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_hw_init()
412 VCN, GET_INST(VCN, i), in jpeg_v4_0_3_hw_init()
498 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
523 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
545 int jpeg_inst = GET_INST(JPEG, inst); in jpeg_v4_0_3_start_inst()
637 int jpeg_inst = GET_INST(JPEG, inst); in jpeg_v4_0_3_stop_inst()
1216 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_set_dec_ring_funcs()
1298 NULL, 0, GET_INST(VCN, jpeg_inst), in jpeg_v4_0_3_inst_query_ras_error_count()
[all …]
A Djpeg_v5_0_1.c170 jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_sw_init()
267 jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_hw_init()
360 int jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_init_inst()
381 int jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_deinit_inst()
397 int jpeg_inst = GET_INST(JPEG, ring->me); in jpeg_v5_0_1_init_jrbc()
466 jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_start_sriov()
642 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), in jpeg_v5_0_1_dec_ring_set_wptr()
659 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), in jpeg_v5_0_1_is_idle()
679 ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), in jpeg_v5_0_1_wait_for_idle()
813 int jpeg_inst = GET_INST(JPEG, ring->me); in jpeg_v5_0_1_core_stall_reset()
[all …]
A Dvcn_v5_0_1.c122 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_sw_init()
246 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_hw_init()
363 vcn_inst = GET_INST(VCN, inst); in vcn_v5_0_1_mc_resume()
560 vcn_inst = GET_INST(VCN, vinst->inst); in vcn_v5_0_1_pause_dpg_mode()
611 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v5_0_1_start_dpg_mode()
745 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_start_sriov()
920 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_start()
1068 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v5_0_1_stop_dpg_mode()
1106 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_stop()
1227 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v5_0_1_unified_ring_set_wptr()
[all …]
A Dvcn_v4_0_3.c188 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_sw_init()
302 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_hw_init_inst()
465 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
656 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_disable_clock_gating()
803 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_enable_clock_gating()
1023 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start_sriov()
1196 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start()
1402 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_stop()
1670 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_set_unified_ring_funcs()
1922 inst_id = GET_INST(VCN, i); in vcn_v4_0_3_dump_ip_state()
[all …]
A Damdgpu_vcn.h146 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
149 VCN, GET_INST(VCN, inst_idx), \
198 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
201 VCN, GET_INST(VCN, inst_idx), \
A Dgmc_v9_0.c882 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
884 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
895 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
897 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
910 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
912 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
925 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
927 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
A Dsdma_v4_4_2.c119 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset()
1743 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); in sdma_v4_4_2_soft_reset_engine()
2040 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state()
2045 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state()
2187 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs()
2459 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_query_ras_error_count()
2497 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_reset_ras_error_count()
A Dsoc15_common.h28 #define GET_INST(ip, inst) \ macro
A Dnbio_v7_9.c79 dev_inst = GET_INST(SDMA0, instance); in nbio_v7_9_sdma_doorbell_range()
A Damdgpu_jpeg.c496 inst_id = GET_INST(JPEG, i); in amdgpu_jpeg_dump_ip_state()
A Dgmc_v11_0.c237 1 << vmid, GET_INST(GC, 0)); in gmc_v11_0_flush_gpu_tlb()
A Dgmc_v12_0.c311 1 << vmid, GET_INST(GC, 0)); in gmc_v12_0_flush_gpu_tlb()
A Dgmc_v10_0.c276 1 << vmid, GET_INST(GC, 0)); in gmc_v10_0_flush_gpu_tlb()
A Damdgpu_device.c792 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_rreg()
923 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_wreg()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_12_ppt.c310 xcc_id = GET_INST(GC, 0); in smu_v13_0_12_get_smu_metrics_data()
378 inst = GET_INST(VCN, k); in smu_v13_0_12_get_xcp_metrics()
402 inst = GET_INST(GC, k); in smu_v13_0_12_get_xcp_metrics()
457 xcc_id = GET_INST(GC, i); in smu_v13_0_12_get_gpu_metrics()
465 inst = GET_INST(VCN, i); in smu_v13_0_12_get_gpu_metrics()
488 gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0); in smu_v13_0_12_get_gpu_metrics()
531 inst = GET_INST(VCN, k); in smu_v13_0_12_get_gpu_metrics()
547 inst = GET_INST(GC, k); in smu_v13_0_12_get_gpu_metrics()
A Dsmu_v13_0_6_ppt.c1213 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
2611 inst = GET_INST(VCN, k); in smu_v13_0_6_get_xcp_metrics()
2639 inst = GET_INST(GC, k); in smu_v13_0_6_get_xcp_metrics()
2737 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2745 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
2772 version) >> GET_INST(GC, 0); in smu_v13_0_6_get_gpu_metrics()
2844 inst = GET_INST(VCN, k); in smu_v13_0_6_get_gpu_metrics()
2862 inst = GET_INST(GC, k); in smu_v13_0_6_get_gpu_metrics()
/drivers/gpu/drm/amd/amdkfd/
A Dkfd_device.c706 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()

Completed in 2185 milliseconds