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Searched refs:GET_SHIFT (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/renesas/
A Dr9a09g077-cpg.c40 #define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val) macro
183 GET_SHIFT(core->conf), in r9a09g077_cpg_div_clk_register()
192 GET_SHIFT(core->conf), in r9a09g077_cpg_div_clk_register()
214 GET_SHIFT(core->conf), in r9a09g077_cpg_mux_clk_register()
A Drzg2l-cpg.c46 #define GET_SHIFT(val) ((val >> 12) & 0xff) macro
181 u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf); in rzg2l_cpg_wait_clk_update_done()
196 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_notifier()
240 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg3s_cpg_div_clk_notifier()
304 val >>= GET_SHIFT(clk_hw_data->conf); in rzg3s_div_clk_recalc_rate()
330 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg3s_div_clk_set_rate()
432 GET_SHIFT(core->conf), in rzg2l_cpg_div_clk_register()
441 GET_SHIFT(core->conf), in rzg2l_cpg_div_clk_register()
461 GET_SHIFT(core->conf), in rzg2l_cpg_mux_clk_register()
476 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_set_parent()
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