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Searched refs:GRL_CFG0 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/mediatek/
A Dmtk_hdmi_regs.h92 #define GRL_CFG0 0x24 macro
A Dmtk_hdmi.c429 regmap_read(hdmi->regs, GRL_CFG0, &val); in mtk_hdmi_hw_aud_set_i2s_fmt()
453 regmap_write(hdmi->regs, GRL_CFG0, val); in mtk_hdmi_hw_aud_set_i2s_fmt()

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