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Searched refs:GRL_CFG1 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/mediatek/
A Dmtk_hdmi_regs.h100 #define GRL_CFG1 0x28 macro
A Dmtk_hdmi.c253 regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0); in mtk_hdmi_hw_enable_dvi_mode()
521 regmap_read(hdmi->regs, GRL_CFG1, &val); in mtk_hdmi_hw_aud_set_input_type()
529 regmap_write(hdmi->regs, GRL_CFG1, val); in mtk_hdmi_hw_aud_set_input_type()

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