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Searched refs:GRL_CFG5 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/mediatek/
A Dmtk_hdmi_regs.h120 #define GRL_CFG5 0x38 macro
A Dmtk_hdmi.c577 regmap_read(hdmi->regs, GRL_CFG5, &val); in mtk_hdmi_hw_aud_set_mclk()
600 regmap_write(hdmi->regs, GRL_CFG5, val); in mtk_hdmi_hw_aud_set_mclk()

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