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Searched refs:HAS_PCH_SPLIT (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_lvds.c249 if (HAS_PCH_SPLIT(display)) { in intel_pre_enable_lvds()
434 if (HAS_PCH_SPLIT(display)) { in intel_lvds_compute_config()
865 if (HAS_PCH_SPLIT(display)) in intel_lvds_init()
872 if (HAS_PCH_SPLIT(display)) { in intel_lvds_init()
912 if (HAS_PCH_SPLIT(display)) { in intel_lvds_init()
A Dg4x_hdmi.c40 if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range) in intel_hdmi_prepare()
138 if (HAS_PCH_SPLIT(display)) { in g4x_hdmi_compute_config()
187 if (!HAS_PCH_SPLIT(display) && in intel_hdmi_get_config()
716 if (HAS_PCH_SPLIT(display)) { in g4x_hdmi_init()
A Dintel_crt.c201 if (!HAS_PCH_SPLIT(display)) in intel_crt_set_dpms()
485 bool turn_off_dac = HAS_PCH_SPLIT(display); in ilk_crt_detect_hotplug()
584 if (HAS_PCH_SPLIT(display)) in intel_crt_detect_hotplug()
1013 if (HAS_PCH_SPLIT(display)) in intel_crt_init()
1103 if (HAS_PCH_SPLIT(display)) { in intel_crt_init()
A Dintel_pch.h54 #define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE) macro
A Dintel_dp_aux.c802 } else if (HAS_PCH_SPLIT(display)) { in intel_dp_aux_init()
817 else if (HAS_PCH_SPLIT(display)) in intel_dp_aux_init()
A Dg4x_dp.c71 } else if (HAS_PCH_SPLIT(display)) { in g4x_dp_set_clock()
1219 if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A) in g4x_dp_compute_config()
1362 (HAS_PCH_SPLIT(display) && port != PORT_A)) { in g4x_dp_init()
A Dintel_sdvo.c220 if (HAS_PCH_SPLIT(display)) { in intel_sdvo_write_sdvox()
1368 if (HAS_PCH_SPLIT(display)) { in intel_sdvo_compute_config()
3365 if (HAS_PCH_SPLIT(display)) in is_sdvo_port_valid()
3422 if (HAS_PCH_SPLIT(display)) { in intel_sdvo_init()
A Dintel_display_irq.c1471 if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) && in gen8_de_irq_handler()
2019 if (HAS_PCH_SPLIT(i915)) in gen8_display_irq_reset()
2248 else if (HAS_PCH_SPLIT(display)) in gen8_de_irq_postinstall()
A Dintel_pps.c1791 if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton) in intel_pps_setup()
1842 if (HAS_PCH_SPLIT(display)) { in assert_pps_unlocked()
A Dintel_dpll.c382 else if (HAS_PCH_SPLIT(display)) in i9xx_pll_refclk()
1798 else if (HAS_PCH_SPLIT(display)) in intel_dpll_init_clock_hook()
A Dintel_hotplug_irq.c166 (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display))) in intel_hpd_init_pins()
A Dintel_hdmi.c993 else if (HAS_PCH_SPLIT(display)) in intel_hdmi_set_gcp_infoframe()
1018 else if (HAS_PCH_SPLIT(display)) in intel_hdmi_read_gcp_infoframe()
A Dintel_display_debugfs.c97 else if (HAS_PCH_SPLIT(display)) in i915_sr_status()
A Dintel_display_device.c1789 if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) { in __intel_display_device_info_runtime_init()
A Dintel_backlight.c1832 } else if (HAS_PCH_SPLIT(display)) { in intel_backlight_init_funcs()
A Dintel_display.c6586 } else if (HAS_PCH_SPLIT(display)) { in intel_pipe_fastset()
7755 } else if (HAS_PCH_SPLIT(display)) { in intel_setup_outputs()
8127 } else if (HAS_PCH_SPLIT(display)) { in intel_init_display_hooks()
A Dintel_bios.c2884 !HAS_PCH_SPLIT(display)); in init_vbt_defaults()
A Dintel_cdclk.c3597 else if (HAS_PCH_SPLIT(display)) in intel_read_rawclk()
A Di9xx_wm.c4145 if (HAS_PCH_SPLIT(display)) { in i9xx_wm_init()

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