| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.h | 76 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
179 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
180 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
181 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
677 uint32_t HDMI_ACR_PACKET_CONTROL; member
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| A D | dce_stream_encoder.c | 1282 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in dce110_se_setup_hdmi_audio()
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| /drivers/gpu/drm/radeon/ |
| A D | evergreen_hdmi.c | 82 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
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| A D | rv770d.h | 693 #define HDMI_ACR_PACKET_CONTROL 0x740c macro
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| A D | evergreend.h | 538 #define HDMI_ACR_PACKET_CONTROL 0x703c macro
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.h | 67 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
160 uint32_t HDMI_ACR_PACKET_CONTROL; member
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| A D | dcn10_stream_encoder.c | 1268 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in enc1_se_setup_hdmi_audio()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 101 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| A D | dcn314_dio_stream_encoder.h | 70 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| A D | dcn35_dio_stream_encoder.h | 68 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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| /drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| A D | dcn30_dio_stream_encoder.h | 69 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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| A D | dcn30_dio_stream_encoder.c | 774 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in enc3_se_setup_hdmi_audio()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | dce_v10_0.c | 1673 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v10_0_afmt_setmode()
1676 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v10_0_afmt_setmode()
1678 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v10_0_afmt_setmode()
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| A D | dce_v11_0.c | 1722 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v11_0_afmt_setmode()
1725 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v11_0_afmt_setmode()
1727 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v11_0_afmt_setmode()
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| A D | dce_v6_0.c | 1494 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v6_0_audio_set_acr()
1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, in dce_v6_0_audio_set_acr()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 194 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 283 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
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