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Searched refs:HDMI_CONTROL (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c129 REG_UPDATE_6(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
144 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
148 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
155 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
159 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
165 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
178 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
221 REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1); in enc35_stream_encoder_hdmi_set_stream_attribute()
224 REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
[all …]
A Ddcn35_dio_stream_encoder.h50 SRI(HDMI_CONTROL, DIG, id), \
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.c141 REG_UPDATE_6(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
156 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
160 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
167 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
171 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
177 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
822 REG_UPDATE(HDMI_CONTROL, in enc401_set_dynamic_metadata()
838 REG_UPDATE(HDMI_CONTROL, in enc401_set_dynamic_metadata()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c183 REG_UPDATE_6(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
194 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc314_stream_encoder_hdmi_set_stream_attribute()
198 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
209 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
213 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
219 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
232 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
244 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
A Ddcn314_dio_stream_encoder.h52 SRI(HDMI_CONTROL, DIG, id), \
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c141 REG_UPDATE_6(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
156 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
160 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
167 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
171 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
177 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.c618 REG_UPDATE_6(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
629 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc3_stream_encoder_hdmi_set_stream_attribute()
633 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
637 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
644 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
648 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
654 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
667 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
679 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
A Ddcn30_dio_stream_encoder.h51 SRI(HDMI_CONTROL, DIG, id), \
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.c557 REG_UPDATE_3(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
562 REG_UPDATE_5(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
576 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
580 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
587 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
591 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
597 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
611 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
623 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
1029 REG_UPDATE_5(HDMI_CONTROL, in dce110_reset_hdmi_stream_attribute()
[all …]
A Ddce_stream_encoder.h68 SRI(HDMI_CONTROL, DIG, id), \
136 SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
137 SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
138 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
139 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
298 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
299 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
308 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
309 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
667 uint32_t HDMI_CONTROL; member
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_stream_encoder.c503 REG_UPDATE_6(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
514 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc1_stream_encoder_hdmi_set_stream_attribute()
519 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
525 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
534 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
540 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
548 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
563 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
575 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
1046 REG_UPDATE_5(HDMI_CONTROL, in enc1_reset_hdmi_stream_attribute()
A Ddcn10_stream_encoder.h56 SRI(HDMI_CONTROL, DIG, id), \
148 uint32_t HDMI_CONTROL; member
/drivers/gpu/drm/radeon/
A Devergreen_hdmi.c326 val = RREG32(HDMI_CONTROL + offset); in dce4_hdmi_set_color_depth()
353 WREG32(HDMI_CONTROL + offset, val); in dce4_hdmi_set_color_depth()
A Drv770d.h681 #define HDMI_CONTROL 0x7400 macro
A Devergreend.h520 #define HDMI_CONTROL 0x7030 macro
/drivers/gpu/drm/amd/amdgpu/
A Ddce_v10_0.c1613 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v10_0_afmt_setmode()
1614 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v10_0_afmt_setmode()
1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v10_0_afmt_setmode()
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v10_0_afmt_setmode()
A Ddce_v11_0.c1662 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v11_0_afmt_setmode()
1663 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v11_0_afmt_setmode()
1668 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1669 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v11_0_afmt_setmode()
1674 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1675 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v11_0_afmt_setmode()
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h83 SRI_ARR(HDMI_CONTROL, DIG, id), \
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h177 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h266 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \

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