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Searched refs:HDMI_GC_CONT (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.h140 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
225 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
409 uint8_t HDMI_GC_CONT; member
541 uint32_t HDMI_GC_CONT; member
A Ddce_stream_encoder.c630 HDMI_GC_CONT, 1, in dce110_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c252 HDMI_GC_CONT, 1, in enc314_stream_encoder_hdmi_set_stream_attribute()
A Ddcn314_dio_stream_encoder.h123 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c198 HDMI_GC_CONT, 1, in enc35_stream_encoder_hdmi_set_stream_attribute()
A Ddcn35_dio_stream_encoder.h124 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c210 HDMI_GC_CONT, 1, in enc32_stream_encoder_hdmi_set_stream_attribute()
A Ddcn32_dio_stream_encoder.h44 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.h45 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
A Ddcn401_dio_stream_encoder.c210 HDMI_GC_CONT, 1, in enc401_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_stream_encoder.h213 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
420 type HDMI_GC_CONT;\
A Ddcn10_stream_encoder.c582 HDMI_GC_CONT, 1, in enc1_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/radeon/
A Devergreen_hdmi.c316 HDMI_GC_CONT); /* send general control packets every frame */ in dce4_set_vbi_packet()
A Drv770d.h706 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ macro
A Devergreend.h556 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ macro
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.h124 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
A Ddcn30_dio_stream_encoder.c687 HDMI_GC_CONT, 1, in enc3_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/include/asic_reg/dce/
A Ddce_11_0_enum.h2092 typedef enum HDMI_GC_CONT { enum
2095 } HDMI_GC_CONT; typedef
A Ddce_11_2_enum.h2555 typedef enum HDMI_GC_CONT { enum
2558 } HDMI_GC_CONT; typedef
/drivers/gpu/drm/amd/amdgpu/
A Ddce_v6_0.c1479 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); in dce_v6_0_audio_set_vbi_packet()
A Ddce_v10_0.c1636 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packet… in dce_v10_0_afmt_setmode()
A Ddce_v11_0.c1685 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packet… in dce_v11_0_afmt_setmode()
/drivers/gpu/drm/amd/include/
A Dsoc24_enum.h6809 typedef enum HDMI_GC_CONT { enum
6812 } HDMI_GC_CONT; typedef
A Dvega10_enum.h3965 typedef enum HDMI_GC_CONT { enum
3968 } HDMI_GC_CONT; typedef
A Dnavi10_enum.h6434 typedef enum HDMI_GC_CONT { enum
6437 } HDMI_GC_CONT; typedef

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