Home
last modified time | relevance | path

Searched refs:HDMI_NUM_TX_CHANNEL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/hdmi/
A Dhdmi_phy_8996.c27 #define HDMI_NUM_TX_CHANNEL 4 macro
42 u32 tx_lx_lane_mode[HDMI_NUM_TX_CHANNEL];
43 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
63 u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
65 u32 tx_lx_vmode_ctrl1[HDMI_NUM_TX_CHANNEL];
66 u32 tx_lx_vmode_ctrl2[HDMI_NUM_TX_CHANNEL];
68 u32 tx_lx_hp_pd_enables[HDMI_NUM_TX_CHANNEL];
317 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) in pll_calculate()
383 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in pll_calculate()
424 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8996_pll_set_clk_rate()
[all …]
A Dhdmi_phy_8998.c28 #define HDMI_NUM_TX_CHANNEL 4 macro
62 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
63 u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
65 u32 tx_lx_pre_driver_1[HDMI_NUM_TX_CHANNEL];
66 u32 tx_lx_pre_driver_2[HDMI_NUM_TX_CHANNEL];
67 u32 tx_lx_res_code_offset[HDMI_NUM_TX_CHANNEL];
352 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) in pll_calculate()
467 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
532 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
552 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
[all …]

Completed in 7 milliseconds