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Searched refs:HECI_H_GS1_ER_PREP (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/xe/regs/
A Dxe_gsc_regs.h47 #define HECI_H_GS1_ER_PREP REG_BIT(0) macro
/drivers/gpu/drm/xe/
A Dxe_gsc.c592 u32 gs1_set = prep ? HECI_H_GS1_ER_PREP : 0; in xe_gsc_wa_14015076503()
593 u32 gs1_clr = prep ? 0 : HECI_H_GS1_ER_PREP; in xe_gsc_wa_14015076503()
/drivers/gpu/drm/i915/gt/
A Dintel_reset.c744 0, HECI_H_GS1_ER_PREP); in wa_14015076503_start()
764 HECI_H_GS1_ER_PREP, 0); in wa_14015076503_end()
/drivers/gpu/drm/i915/
A Di915_reg.h289 #define HECI_H_GS1_ER_PREP REG_BIT(0) macro

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