Searched refs:ICE_M (Results 1 – 5 of 5) sorted by relevance
| /drivers/net/ethernet/intel/ice/ |
| A D | ice_hw_autogen.h | 21 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
25 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
27 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
36 #define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0)
38 #define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
49 #define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0)
58 #define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0)
74 #define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0)
88 #define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0)
97 #define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0)
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| A D | ice_ptp_hw.h | 432 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
457 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
459 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
568 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
732 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
733 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
734 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
735 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
755 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
758 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
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| A D | ice_adminq_cmd.h | 77 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
1056 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1081 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1125 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1234 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1643 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
2281 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
2310 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2313 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2340 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
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| A D | ice_osdep.h | 31 #define ICE_M(m, s) ((m ## U) << (s)) macro
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| A D | ice_type.h | 322 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
366 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
1171 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
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