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Searched refs:ICL_PORT_DPLL_DEFAULT (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.h177 ICL_PORT_DPLL_DEFAULT, enumerator
A Dintel_dpll_mgr.c3299 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_update_active_dpll()
3320 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()
3336 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); in icl_compute_combo_phy_dpll()
3352 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()
3414 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3418 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3433 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); in icl_compute_tc_phy_dplls()
3450 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3454 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3480 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
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A Dintel_tc.c1250 is_connected = port_pll_type == ICL_PORT_DPLL_DEFAULT; in tc_phy_is_connected()
1258 port_pll_type == ICL_PORT_DPLL_DEFAULT ? "tbt" : "non-tbt"); in tc_phy_is_connected()
1556 enum icl_port_dpll_id pll_type = ICL_PORT_DPLL_DEFAULT; in tc_port_has_active_streams()
A Dintel_ddi.c4223 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in intel_ddi_get_clock()
4303 return ICL_PORT_DPLL_DEFAULT; in icl_ddi_tc_port_pll_type()
4306 return ICL_PORT_DPLL_DEFAULT; in icl_ddi_tc_port_pll_type()
4316 return ICL_PORT_DPLL_DEFAULT; in intel_ddi_port_pll_type()
4334 port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_ddi_tc_get_clock()
A Dintel_cx0_phy.c3415 return ICL_PORT_DPLL_DEFAULT; in intel_mtl_port_pll_type()

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