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Searched refs:ICP_QAT_UCLO_MAX_CTX (Results 1 – 3 of 3) sorted by relevance

/drivers/crypto/intel/qat/qat_common/
A Dicp_qat_uclo.h12 #define ICP_QAT_UCLO_MAX_CTX 8 macro
13 #define ICP_QAT_UCLO_MAX_UIMAGE (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)
162 struct icp_qat_uclo_page *cur_page[ICP_QAT_UCLO_MAX_CTX];
165 unsigned int new_uaddr[ICP_QAT_UCLO_MAX_CTX];
171 struct icp_qat_uclo_aeslice ae_slices[ICP_QAT_UCLO_MAX_CTX];
A Dqat_hal.c321 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_wr_indr_csr()
352 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_put_sig_event()
368 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_put_wakeup_event()
1500 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_gpr()
1535 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_wr_xfer()
1570 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_rd_xfer()
1590 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_init_nn()
A Dqat_uclo.c820 ICP_QAT_UCLO_MAX_CTX) in qat_uclo_init_reg_sym()
963 ICP_QAT_UCLO_MAX_CTX); s++) { in qat_uclo_set_ae_mode()
1018 ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX); in qat_uclo_parse_uof_obj()
2176 if (ICP_QAT_CTX_MODE(image->ae_mode) == ICP_QAT_UCLO_MAX_CTX) in qat_uclo_wr_uimage_page()
2204 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) in qat_uclo_wr_uimage_page()

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