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/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
A Dirq.c62 irq_reg_store(ID, in irq_clear_all()
208 (void)ID; in irq_raise()
272 irq_ID_t ID; in virq_get_channel_signals() local
276 for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { in virq_get_channel_signals()
300 irq_ID_t ID; in virq_clear_info() local
304 for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { in virq_clear_info()
317 irq_ID_t ID; in virq_get_channel_id() local
337 for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) { in virq_get_channel_id()
406 irq_ID_t ID; in virq_get_irq_id() local
410 for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { in virq_get_irq_id()
[all …]
A Dfifo_monitor.c35 const fifo_monitor_ID_t ID,
40 const fifo_monitor_ID_t ID,
45 const fifo_monitor_ID_t ID, in fifo_channel_get_state() argument
500 const fifo_monitor_ID_t ID, in fifo_switch_get_state() argument
506 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_get_state()
510 (void)ID; in fifo_switch_get_state()
522 const fifo_monitor_ID_t ID, in fifo_monitor_get_state() argument
528 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_get_state()
537 fifo_switch_get_state(ID, sw_id, in fifo_monitor_get_state()
544 const fifo_monitor_ID_t ID, in fifo_monitor_status_valid() argument
[all …]
A Dinput_formatter.c51 const input_formatter_ID_t ID) in input_formatter_rst() argument
56 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_rst()
58 addr = HIVE_IF_SRST_ADDRESS[ID]; in input_formatter_rst()
59 rst = HIVE_IF_SRST_MASK[ID]; in input_formatter_rst()
65 if (!HIVE_IF_BIN_COPY[ID]) { in input_formatter_rst()
73 const input_formatter_ID_t ID) in input_formatter_get_alignment() argument
75 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_alignment()
81 const input_formatter_ID_t ID, in input_formatter_set_fifo_blocking_mode() argument
87 if (!HIVE_IF_BIN_COPY[ID]) { in input_formatter_set_fifo_blocking_mode()
88 input_formatter_reg_store(ID, in input_formatter_set_fifo_blocking_mode()
[all …]
A Dsp_private.h17 const sp_ID_t ID, in sp_ctrl_store() argument
21 assert(ID < N_SP_ID); in sp_ctrl_store()
28 const sp_ID_t ID, in sp_ctrl_load() argument
31 assert(ID < N_SP_ID); in sp_ctrl_load()
37 const sp_ID_t ID, in sp_ctrl_getbit() argument
99 (void)ID; in sp_dmem_store_uint8()
111 (void)ID; in sp_dmem_store_uint16()
123 (void)ID; in sp_dmem_store_uint32()
134 (void)ID; in sp_dmem_load_uint8()
144 (void)ID; in sp_dmem_load_uint16()
[all …]
A Dgp_device.c15 const gp_device_ID_t ID, in gp_device_get_state() argument
18 assert(ID < N_GP_DEVICE_ID); in gp_device_get_state()
21 state->syncgen_enable = gp_device_reg_load(ID, in gp_device_get_state()
25 state->syncgen_pause = gp_device_reg_load(ID, in gp_device_get_state()
27 state->nr_frames = gp_device_reg_load(ID, in gp_device_get_state()
29 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
31 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
39 state->isel_sof = gp_device_reg_load(ID, in gp_device_get_state()
41 state->isel_eof = gp_device_reg_load(ID, in gp_device_get_state()
43 state->isel_sol = gp_device_reg_load(ID, in gp_device_get_state()
[all …]
A Disp_private.h22 const isp_ID_t ID, in isp_ctrl_store() argument
26 assert(ID < N_ISP_ID); in isp_ctrl_store()
37 const isp_ID_t ID, in isp_ctrl_load() argument
40 assert(ID < N_ISP_ID); in isp_ctrl_load()
50 const isp_ID_t ID, in isp_ctrl_getbit() argument
60 const isp_ID_t ID, in isp_ctrl_setbit() argument
71 const isp_ID_t ID, in isp_ctrl_clearbit() argument
82 const isp_ID_t ID, in isp_dmem_store() argument
87 assert(ID < N_ISP_ID); in isp_dmem_store()
120 (void)ID; in isp_dmem_store_uint32()
[all …]
A Devent_fifo_private.h20 assert(ID < N_EVENT_ID); in event_wait_for()
21 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_wait_for()
22 (void)ia_css_device_load_uint32(event_source_addr[ID]); in event_wait_for()
30 event_wait_for(ID); in cnd_event_wait_for()
36 assert(ID < N_EVENT_ID); in event_receive_token()
37 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_receive_token()
44 assert(ID < N_EVENT_ID); in event_send_token()
45 assert(event_sink_addr[ID] != ((hrt_address) - 1)); in event_send_token()
46 ia_css_device_store_uint32(event_sink_addr[ID], token); in event_send_token()
53 assert(ID < N_EVENT_ID); in is_event_pending()
[all …]
A Dinput_system.c85 const rx_ID_t ID, in receiver_set_compression() argument
96 assert(ID < N_RX_ID); in receiver_set_compression()
134 const rx_ID_t ID, in receiver_port_enable() argument
152 const rx_ID_t ID, in is_receiver_port_enabled() argument
161 const rx_ID_t ID, in receiver_irq_enable() argument
170 const rx_ID_t ID, in receiver_get_irq_info() argument
178 const rx_ID_t ID, in receiver_irq_clear() argument
190 const rx_ID_t ID) in receiver_rst() argument
194 assert(ID < N_RX_ID); in receiver_rst()
281 gp_device_reg_store(ID, in input_switch_rst()
[all …]
A Disp.c19 const isp_ID_t ID, in cnd_isp_irq_enable() argument
27 isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, in cnd_isp_irq_enable()
36 unsigned int isp_is_ready(isp_ID_t ID) in isp_is_ready() argument
38 assert(ID < N_ISP_ID); in isp_is_ready()
43 unsigned int isp_is_sleeping(isp_ID_t ID) in isp_is_sleeping() argument
45 assert(ID < N_ISP_ID); in isp_is_sleeping()
50 void isp_start(isp_ID_t ID) in isp_start() argument
52 assert(ID < N_ISP_ID); in isp_start()
56 void isp_wake(isp_ID_t ID) in isp_wake() argument
58 assert(ID < N_ISP_ID); in isp_wake()
[all …]
A Dfifo_monitor_private.h24 const fifo_monitor_ID_t ID, in fifo_switch_set() argument
28 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_set()
29 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_set()
31 (void)ID; in fifo_switch_set()
39 const fifo_monitor_ID_t ID, in fifo_switch_get() argument
42 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_get()
45 (void)ID; in fifo_switch_get()
51 const fifo_monitor_ID_t ID, in fifo_monitor_reg_store() argument
55 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_reg_store()
63 const fifo_monitor_ID_t ID, in fifo_monitor_reg_load() argument
[all …]
/drivers/staging/media/atomisp/pci/css_2401_system/host/
A Dcsi_rx_private.h29 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_load() argument
32 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_load()
43 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_store() argument
47 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_store()
59 const csi_rx_backend_ID_t ID, in csi_rx_be_ctrl_reg_load() argument
62 assert(ID < N_CSI_RX_BACKEND_ID); in csi_rx_be_ctrl_reg_load()
73 const csi_rx_backend_ID_t ID, in csi_rx_be_ctrl_reg_store() argument
139 ID, in csi_rx_fe_ctrl_get_state()
261 ID, i, state->status); in csi_rx_be_ctrl_dump_state()
285 ID, i, in csi_rx_be_ctrl_dump_state()
[all …]
A Dpixelgen_private.h24 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_load() argument
27 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_load()
28 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); in pixelgen_ctrl_reg_load()
38 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_store() argument
42 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_store()
43 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); in pixelgen_ctrl_reg_store()
61 const pixelgen_ID_t ID, in pixelgen_ctrl_get_state() argument
107 pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX); in pixelgen_ctrl_get_state()
109 pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX); in pixelgen_ctrl_get_state()
111 pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX); in pixelgen_ctrl_get_state()
[all …]
A Disys_stream2mmio_private.h35 const stream2mmio_ID_t ID, in stream2mmio_get_state() argument
45 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); in stream2mmio_get_state()
54 const stream2mmio_ID_t ID, in stream2mmio_get_sid_state() argument
101 const stream2mmio_ID_t ID, in stream2mmio_dump_state() argument
111 ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i); in stream2mmio_dump_state()
128 const stream2mmio_ID_t ID, in stream2mmio_reg_load() argument
134 assert(ID < N_STREAM2MMIO_ID); in stream2mmio_reg_load()
146 const stream2mmio_ID_t ID, in stream2mmio_reg_store() argument
150 assert(ID < N_STREAM2MMIO_ID); in stream2mmio_reg_store()
151 assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1); in stream2mmio_reg_store()
[all …]
/drivers/staging/media/atomisp/pci/
A Disp2401_input_system_private.h18 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_load() argument
21 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_load()
22 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_load()
27 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_store() argument
31 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_store()
32 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_store()
135 ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS); in ibuf_ctrl_get_state()
141 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { in ibuf_ctrl_get_state()
143 ID, in ibuf_ctrl_get_state()
163 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { in ibuf_ctrl_dump_state()
[all …]
A Disp2400_input_system_private.h17 const input_system_ID_t ID, in input_system_reg_store() argument
21 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_store()
32 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_load()
39 const rx_ID_t ID, in receiver_reg_store() argument
43 assert(ID < N_RX_ID); in receiver_reg_store()
50 const rx_ID_t ID, in receiver_reg_load() argument
53 assert(ID < N_RX_ID); in receiver_reg_load()
59 const rx_ID_t ID, in receiver_port_reg_store() argument
64 assert(ID < N_RX_ID); in receiver_port_reg_store()
74 const rx_ID_t ID, in receiver_port_reg_load() argument
[all …]
/drivers/scsi/aic7xxx/
A Daic7xxx_osm_pci.c53 ID(ID_AHA_2930CU),
59 ID(ID_AHA_2940),
60 ID(ID_AHA_3940),
61 ID(ID_AHA_398X),
62 ID(ID_AHA_2944),
63 ID(ID_AHA_3944),
64 ID(ID_AHA_4944),
76 ID(ID_AHA_2930U2),
82 ID(ID_AAA_131U2),
84 ID(ID_AHA_29160),
[all …]
A Daiclib.h163 ID(x), \
164 ID((x) | 0x0001000000000000ull), \
165 ID((x) | 0x0002000000000000ull), \
166 ID((x) | 0x0003000000000000ull), \
167 ID((x) | 0x0004000000000000ull), \
168 ID((x) | 0x0005000000000000ull), \
169 ID((x) | 0x0006000000000000ull), \
170 ID((x) | 0x0007000000000000ull), \
171 ID((x) | 0x0008000000000000ull), \
172 ID((x) | 0x0009000000000000ull), \
[all …]
/drivers/gpu/drm/i915/
A Dintel_device_info.c127 #define ID(id) (id) macro
172 INTEL_TGL_GT2_IDS(ID),
176 INTEL_ADLN_IDS(ID),
180 INTEL_RPLS_IDS(ID),
181 INTEL_RPLU_IDS(ID),
182 INTEL_RPLP_IDS(ID),
186 INTEL_RPLU_IDS(ID),
204 INTEL_DG2_D_IDS(ID),
208 INTEL_ARL_H_IDS(ID),
212 INTEL_ARL_U_IDS(ID),
[all …]
/drivers/pinctrl/cirrus/
A Dpinctrl-lochnagar.c76 #define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID) argument
85 #define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID) argument
88 LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
89 LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
90 LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
91 LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
99 #define LN1_PIN(ID) LN_PIN(1, ID) argument
100 #define LN2_PIN(ID) LN_PIN(2, ID) argument
104 LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
106 #define LN1_PINS(ID) LN_PINS(1, ID) argument
[all …]
/drivers/char/agp/
A Dvia-agp.c506 #define ID(x) \ macro
517 ID(PCI_DEVICE_ID_VIA_8501_0),
518 ID(PCI_DEVICE_ID_VIA_8601_0),
520 ID(PCI_DEVICE_ID_VIA_8371_0),
521 ID(PCI_DEVICE_ID_VIA_8633_0),
522 ID(PCI_DEVICE_ID_VIA_XN266),
523 ID(PCI_DEVICE_ID_VIA_8361),
524 ID(PCI_DEVICE_ID_VIA_8363_0),
525 ID(PCI_DEVICE_ID_VIA_8753_0),
528 ID(PCI_DEVICE_ID_VIA_XM266),
[all …]
A Dintel-agp.c831 #define ID(x) \ macro
861 ID(PCI_DEVICE_ID_INTEL_7505_0),
862 ID(PCI_DEVICE_ID_INTEL_7205_0),
877 ID(PCI_DEVICE_ID_INTEL_G33_HB),
878 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
879 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
880 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
882 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
883 ID(PCI_DEVICE_ID_INTEL_G45_HB),
884 ID(PCI_DEVICE_ID_INTEL_G41_HB),
[all …]
/drivers/perf/
A Dfsl_imx9_ddr_perf.c231 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)),
232 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)),
233 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)),
234 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)),
235 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)),
236 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)),
237 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)),
238 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)),
241 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)),
242 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)),
[all …]
/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
A Disp_public.h21 const isp_ID_t ID,
33 const isp_ID_t ID,
46 const isp_ID_t ID,
58 const isp_ID_t ID,
71 const isp_ID_t ID,
84 const isp_ID_t ID,
98 const isp_ID_t ID,
113 const isp_ID_t ID,
128 const isp_ID_t ID,
142 const isp_ID_t ID,
[all …]
A Dsp_public.h21 const sp_ID_t ID,
33 const sp_ID_t ID,
46 const sp_ID_t ID,
58 const sp_ID_t ID,
71 const sp_ID_t ID,
84 const sp_ID_t ID,
98 const sp_ID_t ID,
113 const sp_ID_t ID,
128 const sp_ID_t ID,
142 const sp_ID_t ID,
[all …]
A Dmmu_public.h22 const mmu_ID_t ID,
33 const mmu_ID_t ID);
42 const mmu_ID_t ID);
59 const mmu_ID_t ID, in mmu_reg_store() argument
63 assert(ID < N_MMU_ID); in mmu_reg_store()
64 assert(MMU_BASE[ID] != (hrt_address) - 1); in mmu_reg_store()
65 ia_css_device_store_uint32(MMU_BASE[ID] + reg * sizeof(hrt_data), value); in mmu_reg_store()
78 const mmu_ID_t ID, in mmu_reg_load() argument
81 assert(ID < N_MMU_ID); in mmu_reg_load()
82 assert(MMU_BASE[ID] != (hrt_address) - 1); in mmu_reg_load()
[all …]

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