Searched refs:INSTPM (Results 1 – 10 of 10) sorted by relevance
| /drivers/video/fbdev/i810/ |
| A D | i810_regs.h | 51 #define INSTPM 0x020C0 macro
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| /drivers/gpu/drm/i915/gvt/ |
| A D | mmio_context.c | 61 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
93 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
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| A D | cmd_parser.c | 929 offset == i915_mmio_reg_offset(INSTPM))) in cmd_reg_handler()
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| /drivers/gpu/drm/xe/regs/ |
| A D | xe_engine_regs.h | 95 #define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED) macro
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_workarounds.c | 339 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen6_ctx_workarounds_init()
345 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen7_ctx_workarounds_init()
351 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen8_ctx_workarounds_init()
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| /drivers/gpu/drm/i915/ |
| A D | intel_clock_gating.c | 662 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
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| A D | i915_reg.h | 400 #define INSTPM _MMIO(0x20c0) macro
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| /drivers/gpu/drm/xe/ |
| A D | xe_wa.c | 795 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_display_debugfs.c | 103 sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; in i915_sr_status()
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| A D | i9xx_wm.c | 185 was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; in _intel_set_memory_cxsr()
188 intel_de_write(display, INSTPM, val); in _intel_set_memory_cxsr()
189 intel_de_posting_read(display, INSTPM); in _intel_set_memory_cxsr()
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