Home
last modified time | relevance | path

Searched refs:INT_EN (Results 1 – 16 of 16) sorted by relevance

/drivers/mmc/host/
A Dushc.c114 #define INT_EN 1 macro
184 && test_bit(INT_EN, &ushc->flags) in int_callback()
192 if (!test_bit(INT_EN, &ushc->flags)) in int_callback()
392 set_bit(INT_EN, &ushc->flags); in ushc_enable_sdio_irq()
394 clear_bit(INT_EN, &ushc->flags); in ushc_enable_sdio_irq()
/drivers/clocksource/
A Dtimer-loongson1-pwm.c24 #define INT_EN BIT(5) macro
58 writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL); in ls1x_pwmtimer_start()
/drivers/net/ethernet/oki-semi/pch_gbe/
A Dpch_gbe_main.c725 iowrite32(0, &hw->reg->INT_EN); in pch_gbe_irq_disable()
730 ioread32(&hw->reg->INT_EN)); in pch_gbe_irq_disable()
745 ioread32(&hw->reg->INT_EN)); in pch_gbe_irq_enable()
1259 int_st = int_st & ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1271 int_en = ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1273 &hw->reg->INT_EN); in pch_gbe_intr()
1276 int_st = int_st & ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1290 int_en = ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1304 int_en = ioread32(&hw->reg->INT_EN); in pch_gbe_intr()
1307 iowrite32(int_en, &hw->reg->INT_EN); in pch_gbe_intr()
[all …]
A Dpch_gbe.h39 u32 INT_EN; member
/drivers/net/ethernet/smsc/
A Dsmsc911x.c1232 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_poll()
1234 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_poll()
1526 smsc911x_reg_write(pdata, INT_EN, 0); in smsc911x_disable_irq_chip()
1540 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_irqhandler()
1542 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_irqhandler()
1577 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_irqhandler()
1579 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_irqhandler()
1680 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_open()
1682 smsc911x_reg_write(pdata, INT_EN, temp); in smsc911x_open()
1727 temp = smsc911x_reg_read(pdata, INT_EN); in smsc911x_open()
[all …]
A Dsmsc911x.h140 #define INT_EN 0x5C macro
/drivers/gpu/drm/vc4/
A Dvc4_dsi.c1259 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1262 DSI_PORT_WRITE(INT_EN, in vc4_dsi_host_transfer()
1271 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1274 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1293 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1339 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1708 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); in vc4_dsi_bind()
/drivers/comedi/drivers/
A Dni_pcidio.c249 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC) macro
251 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \ macro
412 flags &= INT_EN; in nidio_interrupt()
711 writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL); in ni_pcidio_cmd()
/drivers/thermal/qcom/
A Dtsens.c738 ret = regmap_field_write(priv->rf[INT_EN], val); in tsens_enable_irq()
748 regmap_field_write(priv->rf[INT_EN], 0); in tsens_disable_irq()
996 priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, in init_common()
997 priv->fields[INT_EN]); in init_common()
998 if (IS_ERR(priv->rf[INT_EN])) { in init_common()
999 ret = PTR_ERR(priv->rf[INT_EN]); in init_common()
A Dtsens-v1.c106 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
A Dtsens-v2.c100 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2),
A Dtsens-v0_1.c302 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
A Dtsens.h179 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ enumerator
/drivers/gpu/drm/imx/dcss/
A Ddcss-ss.c59 #define INT_EN BIT(0) macro
/drivers/scsi/mvsas/
A Dmv_defs.h72 INT_EN = (1U << 1), /* Global int enable */ enumerator
A Dmv_64xx.c426 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
435 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()

Completed in 47 milliseconds