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Searched refs:INT_SEL (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h257 #define INT_SEL(x) ((x) << 24) macro
A Dcikd.h381 #define INT_SEL(x) ((x) << 24) macro
A Dsoc15d.h331 #define INT_SEL(x) ((x) << 24) macro
A Dsid.h510 #define INT_SEL(x) ((x) << 24) macro
A Dgfx_v7_0.c2138 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()
2151 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2180 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
A Dgfx_v8_0.c6123 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()
6138 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6215 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
A Dgfx_v9_4_3.c2899 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_4_3_ring_emit_fence()
A Dgfx_v9_0.c5567 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
/drivers/gpu/drm/radeon/
A Dnid.h1255 #define INT_SEL(x) ((x) << 24) macro
A Dsid.h1769 #define INT_SEL(x) ((x) << 24) macro
A Dcikd.h1842 #define INT_SEL(x) ((x) << 24) macro
A Dr600d.h1680 #define INT_SEL(x) ((x) << 24) macro
A Dni.c1394 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
A Dcik.c3556 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()
3567 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3593 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
A Dr600.c2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
A Dsi.c3372 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()

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