Home
last modified time | relevance | path

Searched refs:IS_DG2 (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/i915/gt/
A Dintel_workarounds.c925 else if (IS_DG2(i915)) in __intel_engine_init_ctx_wa()
1389 if (IS_DG2(gt->i915)) in xehp_init_mcr()
1669 else if (IS_DG2(i915)) in gt_init_workarounds()
2114 else if (IS_DG2(i915)) in intel_engine_init_whitelist()
2222 IS_DG2(i915)) { in rcs_engine_wa_init()
2229 IS_DG2(i915)) { in rcs_engine_wa_init()
2235 if (IS_DG2(i915)) { in rcs_engine_wa_init()
2245 IS_DG2(i915)) { in rcs_engine_wa_init()
2828 IS_DG2(i915)) { in general_render_compute_wa_init()
2839 IS_DG2(i915)) { in general_render_compute_wa_init()
[all …]
A Dintel_gt_ccs_mode.c17 if (!IS_DG2(gt->i915)) in intel_gt_apply_ccs_mode()
A Dintel_gt_mcr.c154 } else if (IS_DG2(i915)) { in intel_gt_mcr_init()
618 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
A Dgen8_engine_cs.c227 IS_DG2(rq->i915)) { in mtl_dummy_pipe_control()
828 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) in gen12_emit_fini_breadcrumb_rcs()
A Dintel_gsc.c178 } else if (IS_DG2(i915)) { in gsc_init_one()
A Dintel_mocs.c466 } else if (IS_DG2(i915)) { in get_mocs_settings()
A Dintel_reset.c649 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
A Dintel_lrc.c1369 IS_DG2(ce->engine->i915)) in gen12_emit_indirect_ctx_rcs()
A Dintel_engine_cs.c886 if (IS_DG2(gt->i915)) { in init_engine_mask()
/drivers/gpu/drm/xe/compat-i915-headers/
A Di915_drv.h49 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) macro
/drivers/gpu/drm/i915/gt/uc/
A Dintel_huc.c309 if (IS_DG2(i915)) { in intel_huc_init_early()
362 if (IS_DG2(gt->i915)) { in check_huc_loading_mode()
A Dintel_guc.c302 IS_DG2(gt->i915)) in guc_ctl_wa_flags()
321 if (IS_DG2(gt->i915) || in guc_ctl_wa_flags()
A Dintel_guc_ads.c863 IS_DG2(gt->i915))) in guc_waklv_init()
A Dintel_guc_submission.c4573 IS_DG2(engine->i915)) in guc_default_vfuncs()
/drivers/gpu/drm/i915/
A Di915_hwmon.c303 if (IS_DG1(i915) || IS_DG2(i915)) in hwm_pcode_read_i1()
354 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; in hwm_in_is_visible()
850 if (IS_DG1(i915) || IS_DG2(i915)) { in hwm_get_preregistration_info()
A Dintel_clock_gating.c750 if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
A Di915_drv.h491 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) macro
A Di915_perf.c2870 if (IS_DG2(i915)) { in gen12_enable_metric_set()
2949 if (IS_DG2(i915)) { in gen12_disable_metric_set()
3197 if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in i915_perf_oa_timestamp_frequency()
A Di915_driver.c425 if (IS_DG2(i915)) { in i915_enable_g8()
/drivers/gpu/drm/i915/soc/
A Dintel_dram.c718 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()

Completed in 74 milliseconds