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Searched refs:ITR_REG_ALIGN (Results 1 – 10 of 10) sorted by relevance

/drivers/net/ethernet/intel/iavf/
A Diavf_txrx.h27 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~IAVF_ITR_MASK) macro
A Diavf_ethtool.c656 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs); in iavf_set_itr_per_queue()
657 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs); in iavf_set_itr_per_queue()
/drivers/net/ethernet/intel/i40e/
A Di40e_txrx.h27 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK) macro
A Di40e_ethtool.c2987 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs); in i40e_set_itr_per_queue()
2988 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs); in i40e_set_itr_per_queue()
/drivers/net/ethernet/intel/ice/
A Dice_txrx.h291 #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK) macro
A Dice_lib.c1861 ITR_REG_ALIGN(itr) >> ICE_ITR_GRAN_S); in __ice_write_itr()
A Dice_ethtool.c4275 ITR_REG_ALIGN(coalesce_usecs)); in ice_print_if_odd_usecs()
A Dice_main.c3533 ITR_REG_ALIGN(ICE_ITR_8K) >> ICE_ITR_GRAN_S); in ice_req_irq_msix_misc()
/drivers/net/ethernet/intel/idpf/
A Didpf_txrx.h459 #define ITR_REG_ALIGN(setting) ((setting) & IDPF_ITR_MASK) macro
A Didpf_txrx.c3950 writel(ITR_REG_ALIGN(itr) >> IDPF_ITR_GRAN_S, in idpf_vport_intr_write_itr()

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