| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 112 unsigned int InterlaceEnable; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 670 unsigned int InterlaceEnable,
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| A D | display_mode_vba_util_32.c | 2068 myPipe[k].InterlaceEnable, in dml32_CalculateVMRowAndSwath()
2142 myPipe[k].InterlaceEnable, in dml32_CalculateVMRowAndSwath()
3203 unsigned int InterlaceEnable, in dml32_CalculateVUpdateAndDynamicMetadataParameters() argument
3232 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) in dml32_CalculateVUpdateAndDynamicMetadataParameters()
3509 myPipe->InterlaceEnable, in dml32_CalculatePrefetchSchedule()
3591 …if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnit… in dml32_CalculatePrefetchSchedule()
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| A D | display_mode_vba_32.c | 437 …chParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->v… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
774 …eepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->v… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2730 …v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode… in dml32_ModeSupportAndSystemConfigurationFull()
3279 …v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.InterlaceEnable = mode_lib->vba.I… in dml32_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 54 unsigned int InterlaceEnable; member
288 int InterlaceEnable,
926 myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
977 if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) in CalculatePrefetchSchedule()
2431 myPipe.InterlaceEnable = v->Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3270 …int DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnit… in CalculateDynamicMetadataParameters() argument
3289 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateDynamicMetadataParameters()
4764 myPipe.InterlaceEnable = v->Interlace[k]; in dml30_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 76 unsigned int InterlaceEnable; member
282 int InterlaceEnable,
935 myPipe->InterlaceEnable,
1009 if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
2608 myPipe.InterlaceEnable = v->Interlace[k];
3412 int InterlaceEnable, argument
3436 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
3697 myPipe.InterlaceEnable = v->Interlace[k];
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 74 unsigned int InterlaceEnable; member
291 int InterlaceEnable,
953 myPipe->InterlaceEnable,
1027 if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
2627 myPipe.InterlaceEnable = v->Interlace[k];
3518 int InterlaceEnable, argument
3542 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
3803 myPipe.InterlaceEnable = v->Interlace[k];
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 53 unsigned int InterlaceEnable; member
746 if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) in CalculatePrefetchSchedule()
779 if (myPipe->InterlaceEnable && !ProgressiveToInterlaceUnitInOPP) in CalculatePrefetchSchedule()
2148 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3442 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in CalculatePrefetchSchedulePerPlane()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 118 unsigned int InterlaceEnable; member
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| A D | dml2_core_dcn4_calcs.c | 2930 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
3008 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
4798 unsigned int InterlaceEnable, in CalculateVUpdateAndDynamicMetadataParameters() argument
4824 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateVUpdateAndDynamicMetadataParameters()
5165 p->myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
5246 …if (p->OutputFormat == dml2_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlac… in CalculatePrefetchSchedule()
7421 …myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream… in dml_core_ms_prefetch_check()
8885 …s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descript… in dml_core_mode_support()
10673 …s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descr… in dml_core_mode_programming()
11189 …myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream… in dml_core_mode_programming()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core.c | 362 dml_uint_t InterlaceEnable,
1065 p->myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
1139 …if (p->OutputFormat == dml_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlace… in CalculatePrefetchSchedule()
1859 dml_uint_t InterlaceEnable, in CalculateVUpdateAndDynamicMetadataParameters() argument
1885 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateVUpdateAndDynamicMetadataParameters()
5131 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
5204 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
6376 myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_prefetch_check()
7660 s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_core_mode_support()
8672 s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_core_mode_programming()
[all …]
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| A D | display_mode_core_structs.h | 465 dml_uint_t InterlaceEnable; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 104 bool InterlaceEnable,
487 bool InterlaceEnable, in CalculatePrefetchSchedule()
537 if (OutputFormat == dm_420 || (InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) in CalculatePrefetchSchedule()
570 if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP) in CalculatePrefetchSchedule()
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| A D | display_mode_vba_20v2.c | 129 bool InterlaceEnable,
579 bool InterlaceEnable, in CalculatePrefetchSchedule()
633 if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP) in CalculatePrefetchSchedule()
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