Searched refs:L3_PWM_TIMER_INIT_VAL_MASK (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/xe/ |
| A D | xe_tuning.c | 34 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
35 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
39 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
40 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
113 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
114 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
132 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
133 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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| /drivers/gpu/drm/xe/regs/ |
| A D | xe_gt_regs.h | 417 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_workarounds.c | 682 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()
683 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
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| A D | intel_gt_regs.h | 1008 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro
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