Home
last modified time | relevance | path

Searched refs:LANE_COUNT_DP_MAX (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_training.h83 union lane_status ln_status[LANE_COUNT_DP_MAX],
85 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
113 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
114 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
161 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
162 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
A Dlink_dp_training_fixed_vs_pe_retimer.c46 union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]) in dp_fixed_vs_pe_read_lane_adjust() argument
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
74 const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX], in dp_fixed_vs_pe_set_retimer_lane_settings() argument
168 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
327 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in dp_perform_fixed_vs_pe_training_sequence()
329 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
457 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
458 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
A Dlink_dp_training_fixed_vs_pe_retimer.h38 const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],
43 union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]);
A Dlink_dp_training_128b_132b.c80 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_channel_eq_done_sequence()
81 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_channel_eq_done_sequence()
165 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_cds_done_sequence()
166 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_cds_done_sequence()
A Dlink_dp_training_8b_10b.c231 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_8b_10b_clock_recovery_sequence()
233 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_clock_recovery_sequence()
352 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
353 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
470 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_perform_8b_10b_link_training()
A Dlink_dp_training_dpia.c300 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_non_transparent()
302 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_non_transparent()
466 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_transparent()
468 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_transparent()
596 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_non_transparent()
597 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_non_transparent()
740 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_transparent()
741 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_transparent()
A Dlink_dp_training.c303 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in maximize_lane_settings() argument
347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
361 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_hw_to_dpcd_lane_settings()
597 union lane_status ln_status[LANE_COUNT_DP_MAX], in dp_get_lane_status_and_lane_adjust() argument
599 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], in dp_get_lane_status_and_lane_adjust() argument
681 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in override_lane_settings() argument
692 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_lane_settings()
750 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_training_settings()
855 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], in dp_decide_lane_settings() argument
861 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_decide_lane_settings()
[all …]
/drivers/gpu/drm/amd/display/include/
A Dlink_service_types.h114 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
115 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];
/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_dio.h54 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
A Dlink_hwss_dpia.c82 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dpia_lane_settings() argument
A Dlink_hwss_hpo_dp.c161 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_dp_lane_settings() argument
A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c179 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_fixed_vs_pe_retimer_dp_lane_settings() argument
A Dlink_hwss_dio.c220 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dp_lane_settings() argument
/drivers/gpu/drm/amd/display/dc/inc/
A Dlink_hwss.h65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/drivers/gpu/drm/amd/display/dc/virtual/
A Dvirtual_link_encoder.c65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {} in virtual_link_encoder_dp_set_lane_settings() argument
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dlink_encoder.h133 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.h283 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
A Ddce_link_encoder.c1323 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dce110_link_encoder_dp_set_lane_settings() argument
/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c649 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0}; in dp_set_test_pattern()
817 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) in dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.h618 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
A Ddcn10_link_encoder.c1101 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dcn10_link_encoder_dp_set_lane_settings() argument
/drivers/gpu/drm/amd/display/dc/
A Ddc_dp_types.h38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR enumerator
A Ddc.h1541 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c1209 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in poll_for_allocation_change_trigger()

Completed in 84 milliseconds