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Searched refs:LANE_COUNT_FOUR (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
A Dlink_hwss_dio_fixed_vs_pe_retimer.c32 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg()
168 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_dio_fixed_vs_pe_retimer_dp_link_output()
/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_capability.c78 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
79 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
81 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
83 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
86 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
91 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
93 {LANE_COUNT_FOUR, LINK_RATE_LOW},
484 case LANE_COUNT_FOUR: in reduce_lane_count()
536 return LANE_COUNT_FOUR; in increase_lane_count()
968 link_setting->lane_count = LANE_COUNT_FOUR; in link_decide_link_settings()
A Dlink_dp_training_fixed_vs_pe_retimer.c305 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence()
A Dlink_dp_training.c450 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0) in dp_get_cr_failure()
452 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0) in dp_get_cr_failure()
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c121 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc314_stream_encoder_dvi_set_stream_attribute()
161 cntl.lanes_number = LANE_COUNT_FOUR; in enc314_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c67 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc35_stream_encoder_dvi_set_stream_attribute()
106 cntl.lanes_number = LANE_COUNT_FOUR; in enc35_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc32_stream_encoder_dvi_set_stream_attribute()
119 cntl.lanes_number = LANE_COUNT_FOUR; in enc32_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/virtual/
A Dvirtual_link_encoder.c90 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in virtual_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.c79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc401_stream_encoder_dvi_set_stream_attribute()
119 cntl.lanes_number = LANE_COUNT_FOUR; in enc401_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.c546 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_hdmi_set_stream_attribute()
663 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in dce110_stream_encoder_dvi_set_stream_attribute()
687 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_lvds_set_stream_attribute()
A Ddce_link_encoder.c968 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_link_encoder_hw_init()
1669 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in dce110_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.c544 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc3_stream_encoder_dvi_set_stream_attribute()
590 cntl.lanes_number = LANE_COUNT_FOUR; in enc3_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table.c232 if (LANE_COUNT_FOUR < cntl->lanes_number) in encoder_control_digx_v3()
278 if (LANE_COUNT_FOUR < cntl->lanes_number) in encoder_control_digx_v4()
477 if (LANE_COUNT_FOUR < cntl->lanes_number) { in transmitter_control_v2()
615 if (LANE_COUNT_FOUR < cntl->lanes_number) { in transmitter_control_v3()
749 if (LANE_COUNT_FOUR < cntl->lanes_number) in transmitter_control_v4()
/drivers/gpu/drm/amd/display/dc/
A Ddc_dp_types.h36 LANE_COUNT_FOUR = 4, enumerator
38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c839 cntl.lanes_number = LANE_COUNT_FOUR; in dcn10_link_encoder_hw_init()
1454 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in dcn10_link_encoder_get_max_link_cap()
A Ddcn10_stream_encoder.c494 cntl.lanes_number = LANE_COUNT_FOUR; in enc1_stream_encoder_hdmi_set_stream_attribute()
614 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc1_stream_encoder_dvi_set_stream_attribute()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_debugfs.c295 case LANE_COUNT_FOUR: in dp_link_settings_write()
429 case LANE_COUNT_FOUR: in dp_mst_link_setting()
3436 case LANE_COUNT_FOUR: in edp_ilr_write()
A Damdgpu_dm.c7524 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; in handle_edid_mgmt()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c869 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_edp_power_control()
991 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_edp_backlight_control()

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