Searched refs:LSC_CHICKEN_BIT_0 (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/xe/ |
| A D | xe_wa.c | 382 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
399 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
449 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
490 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
572 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
594 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
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| /drivers/gpu/drm/xe/regs/ |
| A D | xe_gt_regs.h | 526 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) macro
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_workarounds.c | 2841 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); in general_render_compute_wa_init()
2868 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, in general_render_compute_wa_init()
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| A D | intel_gt_regs.h | 1181 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) macro
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