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Searched refs:MASK (Results 1 – 25 of 57) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dgk20a.h30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
A Dgm20b.c41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_pllg_read_mnp()
254 rem = ((u32)n) & MASK(DFS_DET_RANGE); in gm20b_dvfs_calc_ndiv()
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); in gm20b_clk_init_dvfs()
951 MASK(FUSE_RESERVED_CALIB0_FUSE_REV_WIDTH); in gm20b_clk_init_fused_params()
960 MASK(FUSE_RESERVED_CALIB0_SLOPE_INT_WIDTH)) * 1000 + in gm20b_clk_init_fused_params()
962 MASK(FUSE_RESERVED_CALIB0_SLOPE_FRAC_WIDTH)); in gm20b_clk_init_fused_params()
966 MASK(FUSE_RESERVED_CALIB0_INTERCEPT_INT_WIDTH)) * 1000 + in gm20b_clk_init_fused_params()
[all …]
A Dgk20a.c71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
82 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; in gk20a_pllg_write_mnp()
83 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; in gk20a_pllg_write_mnp()
84 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; in gk20a_pllg_write_mnp()
/drivers/scsi/sym53c8xx_2/
A Dsym_fw2.h228 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
438 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
462 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
521 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
898 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
904 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1269 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1271 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1464 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1675 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
[all …]
A Dsym_fw1.h236 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
453 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
478 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
538 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
949 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
955 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1207 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1390 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1392 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1398 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/
A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
164 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
172 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
A Dddc_regs.h41 DDC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
64 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK, cd),\
81 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK, cd),\
A Dgeneric_regs.h38 GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
A Dhpd_regs.h46 HPD_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
/drivers/dma/dw/
A Dcore.c122 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
123 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
488 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
489 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
512 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
523 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
524 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
527 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); in dw_dma_interrupt()
1118 channel_clear_bit(dw, MASK.XFER, dwc->mask); in dwc_free_chan_resources()
1119 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); in dwc_free_chan_resources()
[all …]
/drivers/gpu/drm/hisilicon/kirin/
A Dkirin_ade_reg.h13 #define MASK(x) (BIT_ULL(x) - 1) macro
17 #define FRM_END_START_MASK MASK(2)
50 #define CH_OVLY_SEL_MASK MASK(2)
99 #define QOSGENERATOR_MODE_MASK MASK(2)
A Dkirin_drm_ade.c103 MASK(1), !!val); in ade_update_reload_bit()
129 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); in ade_init()
130 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); in ade_init()
131 writel(MASK(32), base + ADE_RELOAD_DIS(0)); in ade_init()
132 writel(MASK(32), base + ADE_RELOAD_DIS(1)); in ade_init()
286 MASK(1), 1); in ade_crtc_enable_vblank()
303 MASK(1), 0); in ade_crtc_disable_vblank()
319 MASK(1), 1); in ade_irq_handler()
700 MASK(1), 0); in ade_compositor_routing_disable()
A Ddw_drm_dsi.c351 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); in dsi_set_phy_timer()
352 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); in dsi_set_phy_timer()
353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
357 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), in dsi_set_phy_timer()
359 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), in dsi_set_phy_timer()
A Ddw_dsi_reg.h12 #define MASK(x) (BIT(x) - 1) macro
/drivers/clk/tegra/
A Dclk-tegra-periph.c130 #define MASK(x) (BIT(x) - 1) macro
135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
175 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
182 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
189 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
196 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
203 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
[all …]
/drivers/tty/
A Dn_tty.c135 return ldata->read_buf[MASK(i)]; in read_buf()
140 return &ldata->read_buf[MASK(i)]; in read_buf_addr()
146 return ldata->echo_buf[MASK(i)]; in echo_buf()
574 if (MASK(ldata->echo_commit) == MASK(*tail + 1)) in n_tty_process_echo_ops()
587 if (MASK(ldata->echo_commit) == MASK(*tail + 2)) in n_tty_process_echo_ops()
690 while (MASK(ldata->echo_commit) != MASK(tail)) { in __process_echoes()
966 while (MASK(ldata->read_head) != MASK(ldata->canon_head)) { in eraser()
974 MASK(head) != MASK(ldata->canon_head)); in eraser()
1016 while (MASK(tail) != MASK(ldata->canon_head)) { in eraser()
1285 while (MASK(tail) != MASK(ldata->read_head)) { in n_tty_receive_char_canon()
[all …]
/drivers/scsi/
A Dvmw_pvscsi.h31 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
410 #define PVSCSI_INTR_CMPL_MASK MASK(2)
414 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
416 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
/drivers/gpu/drm/i915/
A Di915_syncmap.c33 #define MASK (KSYNCMAP - 1) macro
111 return (id >> p->height) & MASK; in __sync_branch_idx()
118 return id & MASK; in __sync_leaf_idx()
302 idx = p->prefix >> (above - SHIFT) & MASK; in __sync_set()
/drivers/gpu/nova-core/regs/
A Dmacros.rs293 const MASK: u32 = $name::[<$field:upper _MASK>]; consts
296 let field = ((self.0 & MASK) >> SHIFT);
308 const MASK: u32 = $name::[<$field:upper _MASK>]; consts
310 let value = (u32::from(value) << SHIFT) & MASK;
311 self.0 = (self.0 & !MASK) | value;
/drivers/dma/
A Didma64.c41 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); in idma64_off()
42 channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); in idma64_off()
43 channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); in idma64_off()
44 channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); in idma64_off()
45 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); in idma64_off()
71 channel_set_bit(idma64, MASK(XFER), idma64c->mask); in idma64_chan_init()
72 channel_set_bit(idma64, MASK(ERROR), idma64c->mask); in idma64_chan_init()
/drivers/gpu/drm/nouveau/dispnv04/
A Dcursor.c46 MASK(NV_CIO_CRE_HCUR_ASI) | in nv04_cursor_set_offset()
52 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); in nv04_cursor_set_offset()
A Dhw.h31 #define MASK(field) ( \ macro
35 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
379 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
381 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
/drivers/scsi/aic7xxx/aicasm/
A Daicasm_symbol.c102 case MASK: in symbol_delete()
244 case MASK: in symlist_add()
502 case MASK: in symtable_dump()
629 case MASK: in symtable_dump()
/drivers/char/xilinx_hwicap/
A Dxilinx_hwicap.c124 .MASK = 6,
149 .MASK = 6,
174 .MASK = 6,
199 .MASK = 6,
/drivers/platform/x86/
A Dcompal-laptop.c367 #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \ argument
371 return sysfs_emit(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \
380 ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \

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