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Searched refs:MAX_DWB_PIPES (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h260 struct dwbc *dwbc[MAX_DWB_PIPES];
261 struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
551 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_stream.c487 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
511 ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES); in dc_stream_add_writeback()
554 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_fc_disable_writeback()
559 if (stream->num_wb_info > MAX_DWB_PIPES) { in dc_stream_fc_disable_writeback()
590 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_remove_writeback()
595 if (stream->num_wb_info > MAX_DWB_PIPES) { in dc_stream_remove_writeback()
A Ddc.c3293 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES); in copy_stream_update_to_stream()
/drivers/gpu/drm/amd/display/dc/
A Ddc_stream.h111 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
284 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dhw_shared.h49 #define MAX_DWB_PIPES 1 macro
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c434 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
557 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_disable_writeback()
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1391 for (j = 0; j < MAX_DWB_PIPES; j++) { in dcn30_set_mcif_arb_params()
1418 if (dwb_pipe >= MAX_DWB_PIPES) in dcn30_set_mcif_arb_params()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1610 for (j = 0; j < MAX_DWB_PIPES; j++) { in dcn20_set_mcif_arb_params()
1637 if (dwb_pipe >= MAX_DWB_PIPES) in dcn20_set_mcif_arb_params()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c2540 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
2565 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_disable_writeback()

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