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Searched refs:MAX_MPCC (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
A Ddcn30_mpc.h192 uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \
234 uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \
235 uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \
236 uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \
275 uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \
276 uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \
342 uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \
343 uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \
344 uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \
351 uint32_t MPCC_MCM_1DLUT_CONTROL[MAX_MPCC]; \
[all …]
A Ddcn30_mpc.c1573 for (i = 0; i < MAX_MPCC; i++) in dcn30_mpc_construct()
/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.h89 uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
90 uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
91 uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
98 uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
104 uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
118 uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
120 uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
121 uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
122 uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
123 uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
[all …]
A Ddcn20_mpc.c607 for (i = 0; i < MAX_MPCC; i++) in dcn20_mpc_construct()
/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
A Ddcn401_mpc.h38 uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \
39 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \
40 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \
41 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \
42 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \
43 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \
44 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \
45 uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \
52 uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_MODE[MAX_MPCC]; \
65 uint32_t MPCC_MCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \
[all …]
A Ddcn401_mpc.c640 for (i = 0; i < MAX_MPCC; i++) in dcn401_mpc_construct()
/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.h50 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
51 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
52 uint32_t MPCC_CONTROL[MAX_MPCC]; \
53 uint32_t MPCC_STATUS[MAX_MPCC]; \
54 uint32_t MPCC_OPP_ID[MAX_MPCC]; \
55 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
56 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
57 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
58 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
60 uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
A Ddcn10_mpc.c518 for (i = 0; i < MAX_MPCC; i++) in dcn10_mpc_construct()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dmpc.h58 #define MAX_MPCC 6 macro
318 struct mpcc mpcc_array[MAX_MPCC];
/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_mpc.c123 for (i = 0; i < MAX_MPCC; i++) in dcn201_mpc_construct()
/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
A Ddcn32_mpc.c1049 for (i = 0; i < MAX_MPCC; i++) in dcn32_mpc_construct()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c842 if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id])) in dcn35_init_pipes()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c3701 if (s.dpp_id < MAX_MPCC) in acquire_resource_from_hw_enabled_state()
3705 if (s.bot_mpcc_id < MAX_MPCC) in acquire_resource_from_hw_enabled_state()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1674 if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id])) in dcn10_init_pipes()

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