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Searched refs:MCHBAR_MIRROR_BASE_SNB (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
A Dintel_mchbar_regs.h23 #define MCHBAR_MIRROR_BASE_SNB 0x140000 macro
99 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
140 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
141 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
142 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
209 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
215 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
230 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
243 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
251 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)
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A Dintel_gvt_mmio_table.c706 MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000); in iterate_generic_mmio()
/drivers/gpu/drm/xe/regs/
A Dxe_mchbar_regs.h19 #define MCHBAR_MIRROR_BASE_SNB 0x140000 macro
21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
40 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
/drivers/gpu/drm/xe/
A Dxe_guc_pc.c38 #define MCHBAR_MIRROR_BASE_SNB 0x140000 macro
40 #define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
45 #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)

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