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Searched refs:MCLK (Results 1 – 18 of 18) sorted by relevance

/drivers/spi/
A Dspi-mpc52xx-psc.c26 #define MCLK 20000000 /* PSC port MClk in hz */ macro
93 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
95 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
250 mclken_div = 512000000 / MCLK; in mpc52xx_psc_spi_port_config()
/drivers/media/pci/ddbridge/
A Dddbridge-sx8.c14 static const u32 MCLK = (1550000000 / 12); variable
187 if (p->symbol_rate >= (MCLK / 2)) in start()
209 if (p->symbol_rate >= MCLK / 2) { in start()
244 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
/drivers/video/fbdev/sis/
A Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); in SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); in SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
A Dinit301.c5336 unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0; in SiS_SetCRT2FIFO_300() local
5383 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT2FIFO_300()
5389 data2 = temp - ((colorth * VCLK) / MCLK); in SiS_SetCRT2FIFO_300()
5469 temp = data % (MCLK << 4); in SiS_SetCRT2FIFO_300()
5470 data = data / (MCLK << 4); in SiS_SetCRT2FIFO_300()
/drivers/video/fbdev/matrox/
A Dmatroxfb_Ti3026.c206 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX)) argument
/drivers/video/fbdev/savage/
A Dsavagefb.h210 int MCLK, REFCLK, LCDclk; member
A Dsavagefb_driver.c1087 if (par->MCLK <= 0) { in savagefb_decode_var()
1091 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, in savagefb_decode_var()
1937 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; in savage_init_hw()
1939 par->MCLK); in savage_init_hw()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c120 CLK_MAP(MCLK, CLOCK_FCLK),
/drivers/clk/
A DKconfig266 codec (sometimes known as MCLK).
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.c170 CLK_MAP(MCLK, PPCLK_UCLK),
A Dsienna_cichlid_ppt.c170 CLK_MAP(MCLK, PPCLK_UCLK),
A Dnavi10_ppt.c155 CLK_MAP(MCLK, PPCLK_UCLK),
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.c163 CLK_MAP(MCLK, PPCLK_UCLK),
A Dsmu_v13_0_7_ppt.c154 CLK_MAP(MCLK, PPCLK_UCLK),
A Dsmu_v13_0_0_ppt.c183 CLK_MAP(MCLK, PPCLK_UCLK),
A Dsmu_v13_0_6_ppt.c188 CLK_MAP(MCLK, PPCLK_UCLK),
/drivers/video/fbdev/aty/
A Daty128fb.c300 u16 MCLK; member
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_2_ppt.c147 CLK_MAP(MCLK, PPCLK_UCLK),

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