Searched refs:MCR_REG (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | intel_gt_regs.h | 423 #define XEHP_CULLBIT1 MCR_REG(0x6100)
428 #define VFLSKPD MCR_REG(0x62a8)
434 #define XEHP_FF_MODE2 MCR_REG(0x6604)
473 #define XEHP_CULLBIT2 MCR_REG(0x7030)
478 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
550 #define XEHP_SQCM MCR_REG(0x8724)
748 #define SSMCGCTL9530 MCR_REG(0x9530)
998 #define GEN9_SCRATCH1 MCR_REG(0xb11c)
1001 #define BDW_SCRATCH1 MCR_REG(0xb11c)
1163 #define RT_CTRL MCR_REG(0xe530)
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| /drivers/gpu/drm/i915/gt/uc/ |
| A D | intel_guc_ads.c | 421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()
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| /drivers/gpu/drm/i915/ |
| A D | i915_reg_defs.h | 187 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) macro
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