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Searched refs:MC_SEQ_WR_CTL_2_LP (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dsid.h195 #define MC_SEQ_WR_CTL_2_LP 0xAD6 macro
/drivers/gpu/drm/radeon/
A Dsid.h592 #define MC_SEQ_WR_CTL_2_LP 0x2b58 macro
A Dcikd.h717 #define MC_SEQ_WR_CTL_2_LP 0x2b58 macro
A Dsi_dpm.c5407 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; in si_check_s0_mc_reg_index()
5494 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); in si_initialize_mc_reg_table()
A Dci_dpm.c4418 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; in ci_check_s0_mc_reg_index()
4603 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); in ci_initialize_mc_reg_table()
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c5964 *out_reg = MC_SEQ_WR_CTL_2_LP; in si_check_s0_mc_reg_index()
6051 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); in si_initialize_mc_reg_table()

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