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Searched refs:MG_PLL_DIV0_FBDIV_INT_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_mg_phy_regs.h201 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) macro
A Dintel_dpll_mgr.c3225 m2_int = hw_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()

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