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Searched refs:MISC (Results 1 – 19 of 19) sorted by relevance

/drivers/infiniband/hw/hfi1/
A Dchip_registers.h12 #define MISC (CORE + 0x000000500000) macro
558 #define MISC_CFG_FW_CTRL (MISC + 0x000000001000)
562 #define MISC_CFG_RSA_CMD (MISC + 0x000000000A08)
563 #define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400)
564 #define MISC_CFG_RSA_MU (MISC + 0x000000000A10)
565 #define MISC_CFG_RSA_R2 (MISC + 0x000000000000)
566 #define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200)
567 #define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00)
568 #define MISC_ERR_CLEAR (MISC + 0x000000002010)
569 #define MISC_ERR_MASK (MISC + 0x000000002008)
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/drivers/mfd/
A Dmt6358-irq.c29 MT6357_TOP_GEN(MISC),
40 MT6358_TOP_GEN(MISC),
51 MT6359_TOP_GEN(MISC),
/drivers/firmware/arm_scmi/vendors/imx/
A DKconfig40 tristate "i.MX SCMI MISC EXTENSION"
45 This enables i.MX System MISC control logic such as gpio expander
A Dimx95.rst1267 SCMI_MISC: System Control and Management MISC Vendor Protocol
/drivers/pci/hotplug/
A Dcpqphp.h142 MISC = offsetof(struct ctrl_reg, misc), enumerator
474 misc = readw(ctrl->hpc_reg + MISC); in set_SOGO()
476 writew(misc, ctrl->hpc_reg + MISC); in set_SOGO()
603 misc = readw(ctrl->hpc_reg + MISC); in get_controller_speed()
A Dcpqphp_core.c1153 temp_word = readw(ctrl->hpc_reg + MISC); in cpqhpc_probe()
1155 writew(temp_word, ctrl->hpc_reg + MISC); in cpqhpc_probe()
1269 misc = readw(ctrl->hpc_reg + MISC); in unload_cpqphpd()
1271 writew(misc, ctrl->hpc_reg + MISC); in unload_cpqphpd()
A Dcpqphp_ctrl.c886 misc = readw(ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
900 writew(misc, ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
903 misc = readw(ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
/drivers/usb/misc/sisusbvga/
A Dsisusb_struct.h73 unsigned char MISC; member
/drivers/infiniband/sw/rdmavt/
A Dvt.c280 MISC, enumerator
383 case MISC: in check_support()
/drivers/net/ethernet/realtek/
A Dr8169_main.c390 MISC = 0xf0, /* 8168e only. */ enumerator
2641 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_disable_rxdvgate()
2646 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_enable_rxdvgate()
3141 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
3142 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
3176 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
3197 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
3654 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
/drivers/firmware/imx/
A DKconfig49 tristate "IMX SCMI MISC Protocol driver"
/drivers/clk/samsung/
A Dclk-s5pv210.c62 #define MISC 0xe000 macro
382 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
/drivers/accel/ivpu/
A Divpu_drv.h105 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
A Divpu_drv.c508 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
515 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
A Divpu_hw_btrs.c147 ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config); in read_tile_config_fuse()
536 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_btrs_ats_print_lnl()
A Divpu_hw.c43 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", platform_to_str(platform), platform); in platform_init()
/drivers/video/fbdev/sis/
A Dvstruct.h135 unsigned char MISC; member
A Dinit.c1868 Miscdata = SiS_Pr->SiS_StandTable[StandTableIndex].MISC; in SiS_SetMiscRegs()
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_init.h596 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),

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