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Searched refs:MI_BATCH_BUFFER_END (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/xe/
A Dxe_bb.c68 if (bb->len == 0 || bb->cs[bb->len - 1] != MI_BATCH_BUFFER_END) in __xe_bb_create_job()
69 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in __xe_bb_create_job()
A Dxe_pxp_submit.c298 emit_cmd(pxp->xe, &pxp->vcs_exec.bo->vmap, offset, MI_BATCH_BUFFER_END); in xe_pxp_submit_session_termination()
394 xe_map_wr(xe, batch, len++ * sizeof(u32), u32, MI_BATCH_BUFFER_END); in emit_pxp_heci_cmd()
A Dxe_migrate.c878 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in xe_migrate_copy()
1128 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in xe_migrate_clear()
1430 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in __xe_migrate_update_pgtables()
1450 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in __xe_migrate_update_pgtables()
1659 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in xe_migrate_vram()
A Dxe_lrc.c194 *regs = MI_BATCH_BUFFER_END | BIT(0); in set_offsets()
1109 *state.ptr++ = MI_BATCH_BUFFER_END; in setup_wa_bb()
1596 case MI_BATCH_BUFFER_END: in dump_mi_command()
/drivers/gpu/drm/i915/selftests/
A Digt_spinner.c196 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ in igt_spinner_create_request()
232 *spin->batch = MI_BATCH_BUFFER_END; in igt_spinner_end()
A Di915_request.c977 *cmd = MI_BATCH_BUFFER_END; in empty_batch()
1157 *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */ in recursive_batch()
1179 *cmd = MI_BATCH_BUFFER_END; in recursive_batch_resolve()
1439 *cmd = MI_BATCH_BUFFER_END; in live_sequential_engines()
/drivers/gpu/drm/xe/instructions/
A Dxe_mi_commands.h32 #define MI_BATCH_BUFFER_END __MI_INSTR(0xA) macro
/drivers/gpu/drm/i915/gt/
A Dselftest_engine_cs.c96 cs[0] = MI_BATCH_BUFFER_END; in create_empty_batch()
237 cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END; in create_nop_batch()
A Dselftest_lrc.c256 } while (!err && (lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in live_lrc_layout()
1047 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in store_context()
1049 *cs++ = MI_BATCH_BUFFER_END; in store_context()
1205 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in load_context()
1207 *cs++ = MI_BATCH_BUFFER_END; in load_context()
1370 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in compare_isolation()
A Dintel_renderstate.c124 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); in render_state_setup()
A Dintel_lrc.c100 *regs = MI_BATCH_BUFFER_END; in set_offsets()
1056 *cs++ = MI_BATCH_BUFFER_END | BIT(15); in setup_predicate_disable_wa()
1065 *cs++ = MI_BATCH_BUFFER_END; in setup_predicate_disable_wa()
1457 *cs++ = MI_BATCH_BUFFER_END; in setup_per_ctx_bb()
A Dselftest_ring_submission.c56 *cs++ = MI_BATCH_BUFFER_END; in create_wally()
A Dintel_gpu_commands.h62 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) macro
A Dselftest_hangcheck.c225 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ in hang_create_request()
260 *h->batch = MI_BATCH_BUFFER_END; in hang_fini()
316 *h.batch = MI_BATCH_BUFFER_END; in igt_hang_sanitycheck()
1771 *h.batch = MI_BATCH_BUFFER_END; in igt_reset_queue()
A Dgen7_renderclear.c429 batch_add(&cmds, MI_BATCH_BUFFER_END); in emit_batch()
A Dselftest_tlb.c185 *cs = MI_BATCH_BUFFER_END; in pte_tlbinv()
A Dselftest_workarounds.c612 *cs++ = MI_BATCH_BUFFER_END; in check_dirty_whitelist()
917 *cs++ = MI_BATCH_BUFFER_END; in scrub_whitelisted_registers()
A Dselftest_rps.c720 *cancel = MI_BATCH_BUFFER_END; in live_rps_frequency_cs()
858 *cancel = MI_BATCH_BUFFER_END; in live_rps_frequency_srm()
A Dselftest_execlists.c2757 *cs++ = MI_BATCH_BUFFER_END; in create_gang()
3114 *cs++ = MI_BATCH_BUFFER_END; in create_gpr_user()
3668 cs[n] = MI_BATCH_BUFFER_END; in live_preempt_smoke()
/drivers/gpu/drm/i915/gem/selftests/
A Digt_gem_utils.c87 *cmd = MI_BATCH_BUFFER_END; in igt_emit_store_dw()
A Di915_gem_context.c929 *cmd = MI_BATCH_BUFFER_END; in rpcs_query_batch()
1539 *cmd = MI_BATCH_BUFFER_END; in write_to_scratch()
1645 *cmd = MI_BATCH_BUFFER_END; in read_from_scratch()
1679 *cmd = MI_BATCH_BUFFER_END; in read_from_scratch()
A Di915_gem_client_blt.c250 *cs++ = MI_BATCH_BUFFER_END; in prepare_blit()
/drivers/gpu/drm/i915/gt/uc/
A Dintel_gsc_uc_heci_cmd_submit.c132 *cmd++ = MI_BATCH_BUFFER_END; in emit_gsc_heci_pkt_nonpriv()
/drivers/gpu/drm/i915/
A Di915_cmd_parser.c1486 if (*cmd == MI_BATCH_BUFFER_END) in intel_engine_cmd_parser()
1547 *batch_end = MI_BATCH_BUFFER_END; in intel_engine_cmd_parser()
1552 *cmd = MI_BATCH_BUFFER_END; in intel_engine_cmd_parser()
/drivers/gpu/drm/xe/tests/
A Dxe_migrate.c263 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in xe_migrate_sanity_test()
441 bb->cs[bb->len++] = MI_BATCH_BUFFER_END; in blt_copy()

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