Searched refs:MI_LOAD_REGISTER_REG (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/xe/instructions/ |
| A D | xe_mi_commands.h | 69 #define MI_LOAD_REGISTER_REG (__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3)) macro
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| /drivers/gpu/drm/i915/ |
| A D | i915_cmd_parser.c | 321 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
493 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
1286 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) { in check_cmd()
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| A D | i915_perf.c | 2026 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); in alloc_noa_wait()
2044 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); in alloc_noa_wait()
2064 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); in alloc_noa_wait()
2107 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); in alloc_noa_wait()
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_gpu_commands.h | 178 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) macro
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| A D | intel_lrc.c | 1270 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_timestamp_wa()
1276 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_timestamp_wa()
1314 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_cmd_buf_wa()
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| /drivers/gpu/drm/xe/ |
| A D | xe_gt.c | 262 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO; in emit_wa_job()
283 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO; in emit_wa_job()
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