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Searched refs:MLX5_ST_SZ_DW_MATCH_PARAM (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/
A Dfs_core.h240 #define MLX5_ST_SZ_DW_MATCH_PARAM \ macro
268 u32 val[MLX5_ST_SZ_DW_MATCH_PARAM];
294 u32 match_criteria[MLX5_ST_SZ_DW_MATCH_PARAM];
A Dfs_core.c513 for (i = 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++) in check_valid_spec()
/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dbwc_complex.h8 u32 match_buf[MLX5_ST_SZ_DW_MATCH_PARAM];
A Dbwc_complex.c9 #define HWS_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
1093 for (i = 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++) in hws_bwc_rule_complex_hash_node_get()
/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
A Ddr_fw.c112 u32 val[MLX5_ST_SZ_DW_MATCH_PARAM] = {}; in mlx5dr_fw_create_md_tbl()
A Ddr_cmd.c866 memcpy(in_match_value, fte->val, sizeof(u32) * MLX5_ST_SZ_DW_MATCH_PARAM); in mlx5dr_cmd_set_fte()
A Ddr_types.h20 #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)

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