Searched refs:MMSCH_V1_0_INSERT_DIRECT_WT (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | vce_v4_0.c | 234 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), in vce_v4_0_sriov_start()
236 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), in vce_v4_0_sriov_start()
238 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), in vce_v4_0_sriov_start()
254 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
256 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
261 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
264 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
271 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
274 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
277 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
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| A D | uvd_v7_0.c | 826 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
829 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
840 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
859 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), in uvd_v7_0_sriov_start()
879 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
890 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), in uvd_v7_0_sriov_start()
899 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
903 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
919 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
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| A D | vcn_v2_5.c | 1487 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1490 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1494 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1498 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1501 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1504 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1509 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1514 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1517 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1524 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
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| A D | mmsch_v1_0.h | 138 #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ macro
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