Searched refs:MMSCH_V4_0_INSERT_DIRECT_WT (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v4_0_3.c | 1066 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1071 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1073 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1075 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1077 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1083 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1086 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1089 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1092 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1108 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
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| A D | vcn_v4_0.c | 1422 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1427 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1430 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1433 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1436 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1442 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1445 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1448 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1451 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1487 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
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| A D | mmsch_v4_0.h | 115 #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ macro
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| A D | jpeg_v4_0.c | 474 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
477 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
480 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
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| A D | jpeg_v4_0_3.c | 292 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start_sriov()
294 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start_sriov()
296 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); in jpeg_v4_0_3_start_sriov()
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