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Searched refs:MODE (Results 1 – 25 of 47) sorted by relevance

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/drivers/gpu/drm/nouveau/dispnv04/i2c/
A Dch7006_mode.c134 #define MODE(f, hd, vd, ht, vt, hsynp, vsynp, \ macro
145 MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
146 MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
148 MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
156 MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),
158 MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),
159 MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),
160 MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),
161 MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),
165 MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
[all …]
/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
A Ddcn31_hpo_dp_link_encoder.c99 MODE, DP2_LINK_ACTIVE); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
116 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
125 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
139 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
153 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
167 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
181 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
195 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
209 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
242 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
A Ddcn31_hpo_dp_link_encoder.h115 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
146 type MODE;\
/drivers/media/dvb-frontends/
A Dbcm3510.c506 cmd.ACQUIRE0.MODE = 0x1; in bcm3510_set_frontend()
511 cmd.ACQUIRE0.MODE = 0x2; in bcm3510_set_frontend()
517 cmd.ACQUIRE0.MODE = 0x3; in bcm3510_set_frontend()
520 cmd.ACQUIRE0.MODE = 0x4; in bcm3510_set_frontend()
523 cmd.ACQUIRE0.MODE = 0x5; in bcm3510_set_frontend()
526 cmd.ACQUIRE0.MODE = 0x6; in bcm3510_set_frontend()
529 cmd.ACQUIRE0.MODE = 0x7; in bcm3510_set_frontend()
533 cmd.ACQUIRE0.MODE = 0x8; in bcm3510_set_frontend()
538 cmd.ACQUIRE0.MODE = 0x9; in bcm3510_set_frontend()
A Dbcm3510_priv.h176 u8 MODE :4; member
201 u8 MODE :4; member
/drivers/gpu/drm/nouveau/
A Dnouveau_connector.h75 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, DYNAMIC_2X2),
77 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, STATIC_2X2),
79 NVDEF(NV907D, HEAD_SET_DITHER_CONTROL, MODE, TEMPORAL),
/drivers/soc/bcm/brcmstb/pm/
A Dpm-mips.c40 #define MODE 7 macro
103 ctx->cp0_regs[MODE] = read_c0_brcm_mode(); in brcm_pm_save_cp0_context()
126 write_c0_brcm_mode(ctx->cp0_regs[MODE]); in brcm_pm_restore_cp0_context()
/drivers/gpu/drm/nouveau/dispnv50/
A Dcore507d.c44 NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in core507d_update()
91 NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in core507d_read_caps()
A Dheadca7d.c104 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headca7d_dither()
164 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); in headca7d_curs_set()
209 NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) | in headca7d_olut_set()
A Dwndwca7e.c133 NVVAL(NVCA7E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) | in wndwca7e_ilut_set()
177 NVVAL(NVCA7E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken)); in wndwca7e_ntfy_set()
A Dhead507d.c61 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head507d_dither()
305 NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | in head507d_olut_set()
358 NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) | in head507d_mode()
A Dhead907d.c90 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head907d_dither()
275 NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) | in head907d_olut_set()
368 NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) | in head907d_mode()
A Dovly907e.c45 NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE)); in ovly907e_image_set()
A Dovly827e.c48 NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); in ovly827e_image_set()
A Dheadc37d.c99 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headc37d_dither()
146 NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); in headc37d_curs_set()
A Dcoreca7d.c37 NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in coreca7d_update()
A Dhead917d.c43 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head917d_dither()
A Dcorec37d.c62 NVDEF(NVC37D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in corec37d_update()
A Dovly507e.c71 NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); in ovly507e_image_set()
A Dbase907c.c95 NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode), in base907c_xlut_set()
A Dhead827d.c139 NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | in head827d_olut_set()
/drivers/power/supply/
A Dmax77976_charger.c85 MODE, /* CHG_CNFG_00 */ enumerator
98 [MODE] = REG_FIELD(MAX77976_REG_CHG_CNFG_00, 0, 3),
430 err = regmap_field_write(chg->rfield[MODE], MAX77976_MODE_CHARGER_BUCK); in max77976_configure()
/drivers/gpu/drm/amd/display/dc/hpo/dcn32/
A Ddcn32_hpo_dp_link_encoder.h36 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd_aldebaran.c142 MODE, in kgd_gfx_aldebaran_set_address_watch()
A Damdgpu_amdkfd_gfx_v10.c873 MODE, is_mode_set ? wave_launch_mode : 0); in kgd_gfx_v10_set_wave_launch_mode()
911 MODE, in kgd_gfx_v10_set_address_watch()
925 MODE, in kgd_gfx_v10_set_address_watch()

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