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Searched refs:MP0_C2PMSG_123 (Results 1 – 4 of 4) sorted by relevance

/drivers/accel/amdxdna/
A Dnpu2_regs.c35 #define MP0_C2PMSG_123 0x3810AEC macro
79 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU2_PSP, MP0_C2PMSG_123),
84 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),
A Dnpu5_regs.c35 #define MP0_C2PMSG_123 0x3810AEC macro
79 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU5_PSP, MP0_C2PMSG_123),
84 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123),
A Dnpu6_regs.c35 #define MP0_C2PMSG_123 0x3810AEC macro
79 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123),
84 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
A Dnpu4_regs.c35 #define MP0_C2PMSG_123 0x3810AEC macro
100 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU4_PSP, MP0_C2PMSG_123),
105 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123),

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