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Searched refs:MPNPU_PUB_SCRATCH3 (Results 1 – 5 of 5) sorted by relevance

/drivers/accel/amdxdna/
A Dnpu1_regs.c19 #define MPNPU_PUB_SCRATCH3 0x30100A4 macro
81 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),
86 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),
A Dnpu2_regs.c21 #define MPNPU_PUB_SCRATCH3 0x3010078 macro
80 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU2_REG, MPNPU_PUB_SCRATCH3),
85 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU2_REG, MPNPU_PUB_SCRATCH3),
A Dnpu5_regs.c21 #define MPNPU_PUB_SCRATCH3 0x3010078 macro
80 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU5_REG, MPNPU_PUB_SCRATCH3),
85 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU5_REG, MPNPU_PUB_SCRATCH3),
A Dnpu6_regs.c21 #define MPNPU_PUB_SCRATCH3 0x3010078 macro
80 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
85 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
A Dnpu4_regs.c21 #define MPNPU_PUB_SCRATCH3 0x3010078 macro
101 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU4_REG, MPNPU_PUB_SCRATCH3),
106 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU4_REG, MPNPU_PUB_SCRATCH3),

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