Searched refs:MX (Results 1 – 25 of 47) sorted by relevance
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2 menu "ARM SCMI NXP i.MX Vendor Protocols"5 tristate "i.MX SCMI BBM EXTENSION"9 This enables i.MX System BBM control logic which supports RTC16 tristate "i.MX SCMI CPU EXTENSION"21 This enables i.MX System CPU Protocol to manage cpu28 tristate "i.MX SCMI LMM EXTENSION"33 This enables i.MX System Logical Machine Protocol to40 tristate "i.MX SCMI MISC EXTENSION"45 This enables i.MX System MISC control logic such as gpio expander
8 tristate "i.MX (e)LCDIF LCD controller"20 Those devices are found in various i.MX SoC (including i.MX23,26 tristate "i.MX LCDIFv3 LCD controller"38 Those devices are found in various i.MX SoC (i.MX8MP,
112 #define MX BIT(6) macro127 MX | MY | (par->bgr << 3)); in set_var()139 MX | MV | (par->bgr << 3)); in set_var()
98 #define MX BIT(6) macro112 MX | MY | (par->bgr << 3)); in set_var()124 MX | MV | (par->bgr << 3)); in set_var()
121 #define MX BIT(6) in set_var() macro129 MX | MV | (par->bgr << 3)); in set_var()133 MX | MY | (par->bgr << 3)); in set_var()
3 tristate "DRM Support for Freescale i.MX"11 enable i.MX graphics support45 tristate "Freescale i.MX DRM HDMI"
2 tristate "i.MX interconnect drivers"5 Generic interconnect drivers for i.MX SOCs
2 menu "i.MX PM Domains"5 bool "i.MX GPCv2 PM domains"
47 tristate "NXP i.MX Pixel Pipeline (PXP)"53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
2 tristate "Freescale i.MX LCDC displays"
24 tristate "FEC ethernet controller (of ColdFire and some i.MX CPUs)"36 controller on some Motorola ColdFire and Freescale i.MX/S32 processors.
4 tristate "NXP i.MX DW100 dewarper"
2 menu "i.MX SoC drivers"
72 tristate "Cadence USB3 support on NXP i.MX platforms"76 Say 'Y' or 'M' here if you are building for NXP i.MX
539 bool "i.MX IRQSTEER support"544 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.547 bool "i.MX INTMUX support" if COMPILE_TEST551 Support for the i.MX INTMUX interrupt multiplexer.554 tristate "i.MX MU used as MSI controller"564 Provide a driver for the i.MX Messaging Unit block used as a
30 bool "Amlogic Meson MX SoC Information driver"
77 tristate "i.MX IC Identification Module support"81 i.MX SoCs, providing access to 4 Kbits of programmable88 tristate "i.MX 6/7/8 On-Chip OTP Controller support"100 tristate "i.MX On-Chip OTP Controller support"106 available on i.MX SoCs which has ELE.
51 tristate "Enable i.MX USB glue driver" if EXPERT
105 tristate "i.MX Generic Bus DEVFREQ Driver"109 This adds the generic DEVFREQ driver for i.MX interconnects. It
105 Enables support for the PCIe controller in the i.MX SoCs to106 work in Root Complex mode. The PCI controller on i.MX is based117 Enables support for the PCIe controller in the i.MX SoCs to118 work in endpoint mode. The PCI controller on i.MX is based
267 tristate "Temperature sensor driver for Freescale i.MX SoCs"273 Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.279 tristate "Temperature sensor driver for NXP i.MX SoCs with System Controller"283 Support for Temperature Monitor (TEMPMON) found on NXP i.MX SoCs with
2 # common clock support for NXP i.MX SoC family.
10 This is a DRM bridge implementation for the DRM i.MX IPUv3 driver,
258 tristate "Freescale i.MX RNGA Random Number Generator"263 Generator hardware found on Freescale i.MX processors.271 tristate "Freescale i.MX RNGC Random Number Generator"277 Generator Version C hardware found on some Freescale i.MX
607 bool "Clocksource using i.MX GPT" if COMPILE_TEST612 bool "Clocksource using i.MX TPM" if COMPILE_TEST621 bool "i.MX system counter timer" if COMPILE_TEST624 Enable this option to use i.MX system counter timer as a
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