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Searched refs:N1 (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv40.c63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
162 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
171 &N1, &M1, NULL, NULL, &log2P); in nv40_clk_calc()
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
A Dpllnv04.c151 int M1, N1, M2, N2, log2P; in getMNP_double() local
170 for (N1 = minN1; N1 <= maxN1; N1++) { in getMNP_double()
171 calcclk1 = crystal * N1 / M1; in getMNP_double()
211 *pN1 = N1; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
A Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
39 pv->N1 = N1; in nv04_clk_pll_calc()
A Dmcp77.c57 int N1, M1; in read_pll() local
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
73 clock = ref * N1 / M1; in read_pll()
A Dpll.h9 int *N1, int *M1, int *N2, int *M2, int *P);
A Dnv50.c166 int N1, N2, M1, M2; in read_pll() local
176 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
179 freq = ref * N1 / M1; in read_pll()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv50.c41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
69 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
73 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
A Dnv04.c164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
375 pv.N1 = N1; in nv04_devinit_pll_set()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramnv40.c40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
57 ram->coef = (N1 << 8) | M1; in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
A Dramgf100.c143 int N1, M1, P; in gf100_ram_calc() local
216 &N1, NULL, &M1, &P); in gf100_ram_calc()
225 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
231 &N1, NULL, &M1, &P); in gf100_ram_calc()
238 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
A Dramgk104.c133 int N1, fN1, M1, P1; member
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
703 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in gk104_ram_calc_sddr3()
989 int *N1, int *fN1, int *M1, int *P1, in gk104_pll_calc_hiclk() argument
1014 *N1 = n_ref; in gk104_pll_calc_hiclk()
1025 *N1 = n_ref; in gk104_pll_calc_hiclk()
1037 return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal); in gk104_pll_calc_hiclk()
1066 &ram->N1, &ram->fN1, &ram->M1, &ram->P1, in gk104_ram_calc_xits()
1077 ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, in gk104_ram_calc_xits()
A Dramnv50.c230 int N1, M1, N2, M2, P; in nv50_ram_calc() local
331 &N1, &M1, &N2, &M2, &P); in nv50_ram_calc()
355 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); in nv50_ram_calc()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
A Dpll.h9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
/drivers/dma/dw/
A DKconfig20 tristate "Renesas RZ/N1 DMAMUX driver"
24 Support the Renesas RZ/N1 DMAMUX which is located in front of
/drivers/net/pcs/
A DKconfig29 tristate "Renesas RZ/N1 MII converter"
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
/drivers/net/dsa/
A DKconfig94 tristate "Renesas RZ/N1 A5PSW Ethernet switch support"
100 RZ/N1 SoC.
/drivers/gpu/drm/nouveau/dispnv04/
A Dhw.c211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
272 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && in nouveau_hw_fix_bad_vpll()
280 pv.N1 = pll_lim.vco1.min_n; in nouveau_hw_fix_bad_vpll()
A Dcrtc.c166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
169 pv->N1, pv->M1, pv->log2P); in nv_crtc_calc_state_ext()
/drivers/net/ethernet/stmicro/stmmac/
A DKconfig158 tristate "Renesas RZ/N1 dwmac support"
163 Support for Ethernet controller on Renesas RZ/N1 SoC family.
165 This selects the Renesas RZ/N1 SoC glue layer support for
/drivers/pinctrl/aspeed/
A Dpinctrl-aspeed-g4.c1549 #define N1 190 macro
1550 SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
1551 SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14);
1552 PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14));
1553 FUNC_GROUP_DECL(ADC14, N1);
2067 ASPEED_PINCTRL_PIN(N1),
2520 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
A Dpinctrl-aspeed-g5.c669 #define N1 84 macro
670 SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
671 PIN_DECL_1(N1, GPIOK4, SCL7);
677 FUNC_GROUP_DECL(I2C7, N1, P1);
2056 ASPEED_PINCTRL_PIN(N1),
/drivers/pinctrl/renesas/
A DKconfig297 bool "pin control support for RZ/N1"
303 This selects pinctrl driver for Renesas RZ/N1 devices.
/drivers/mtd/nand/raw/
A DKconfig445 tristate "Renesas R-Car Gen3 & RZ/N1 NAND controller"
449 Gen3 and RZ/N1 SoC families.
/drivers/usb/gadget/udc/
A DKconfig205 available on RZ/N1 Renesas SoCs.
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
A Dphy_lcn.c2000 u16 N1, N2, N3, N4, N5, N6, N; in wlc_lcnphy_rfseq_tbl_adc_pwrup() local
2001 N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0)) in wlc_lcnphy_rfseq_tbl_adc_pwrup()
2013 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80; in wlc_lcnphy_rfseq_tbl_adc_pwrup()

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