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Searched refs:NIX_TXSCH_LVL_TL1 (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/marvell/octeontx2/af/
A Drvu_reg.c36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
A Dcommon.h139 NIX_TXSCH_LVL_TL1 = 0x4, enumerator
A Drvu_nix.c1827 case NIX_TXSCH_LVL_TL1: in handle_txschq_shaper_update()
1949 case NIX_TXSCH_LVL_TL1: in nix_reset_tx_shaping()
2030 case NIX_TXSCH_LVL_TL1: in nix_clear_tx_xoff()
2329 if (lvl == NIX_TXSCH_LVL_TL1) { in nix_smq_flush_fill_ctx()
2416 if (lvl != NIX_TXSCH_LVL_TL1) in nix_smq_flush_enadis_rate()
2420 if (lvl != NIX_TXSCH_LVL_TL1) in nix_smq_flush_enadis_rate()
2558 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, in nix_txschq_free()
2565 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; in nix_txschq_free()
2737 case NIX_TXSCH_LVL_TL1: in is_txschq_shaping_valid()
2884 if (req->lvl == NIX_TXSCH_LVL_TL1) in rvu_mbox_handler_nix_txschq_cfg()
[all …]
A Drvu.c65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
1992 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1994 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()
A Drvu_debugfs.c1888 if (lvl == NIX_TXSCH_LVL_TL1) { in print_tm_topo()
/drivers/net/ethernet/marvell/octeontx2/nic/
A Dqos.c223 else if (parent->level == NIX_TXSCH_LVL_TL1) in otx2_qos_txschq_set_parent_topology()
416 node->level = NIX_TXSCH_LVL_TL1; in otx2_qos_alloc_root()
1063 if (root->level == NIX_TXSCH_LVL_TL1) { in otx2_qos_root_add()
1070 root->level == NIX_TXSCH_LVL_TL1) { in otx2_qos_root_add()
1176 if (parent->level == NIX_TXSCH_LVL_TL1) in otx2_reset_dwrr_prio()
1709 if (root->level != NIX_TXSCH_LVL_TL1) { in otx2_qos_config_txschq()
A Dotx2_common.c692 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; in otx2_txschq_config()
709 } else if (lvl == NIX_TXSCH_LVL_TL1) { in otx2_txschq_config()

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