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Searched refs:NV_PFALCON_FALCON_MAILBOX0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/
A Ddev_falcon_v4.h8 #define NV_PFALCON_FALCON_MAILBOX0 macro
/drivers/gpu/nova-core/
A Dfalcon.rs539 regs::NV_PFALCON_FALCON_MAILBOX0::default() in boot()
570 regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, E::BASE).value(), in boot()
A Dregs.rs202 register!(NV_PFALCON_FALCON_MAILBOX0 @ +0x00000040 {
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
A Dgh100.c49 *mbox0 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX0); in gh100_gsp_lockdown_released()

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