Home
last modified time | relevance | path

Searched refs:NV_PFALCON_FALCON_MAILBOX1 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/
A Ddev_falcon_v4.h11 #define NV_PFALCON_FALCON_MAILBOX1 macro
/drivers/gpu/nova-core/
A Dfalcon.rs545 regs::NV_PFALCON_FALCON_MAILBOX1::default() in boot()
571 regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, E::BASE).value(), in boot()
A Dregs.rs206 register!(NV_PFALCON_FALCON_MAILBOX1 @ +0x00000044 {
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
A Dgh100.c56 u32 mbox1 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX1); in gh100_gsp_lockdown_released()

Completed in 9 milliseconds